[PATCH] D58690: [AArch64] Add code size information on isFPImmLegal

[Evandro Menezes via Phabricator via llvm-commits]

evandro added inline comments.


================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:5407
     IsLegal = AArch64_AM::getFP16Imm(ImmInt) != -1 || Imm.isPosZero();
   // TODO: fmov h0, w0 is also legal, however on't have an isel pattern to
   //       generate that fmov.
----------------
Oops!


================
Comment at: lib/Target/ARM/ARMISelLowering.cpp:4177
   if (CC == ISD::SETUGE || CC == ISD::SETOGE || CC == ISD::SETOLE ||
       CC == ISD::SETULE || CC == ISD::SETGE  || CC == ISD::SETLE)
     CondCode = ARMCC::GE;
----------------
Should this be in another patch?


================
Comment at: lib/Target/ARM/ARMISelLowering.cpp:4182
   else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT ||
            CC == ISD::SETULT || CC == ISD::SETGT  || CC == ISD::SETLT)
     CondCode = ARMCC::GT;
----------------
Ditto.


================
Comment at: lib/Target/ARM/ARMISelLowering.cpp:4188
   if (CC == ISD::SETOLE || CC == ISD::SETULE || CC == ISD::SETOLT ||
       CC == ISD::SETULT || CC == ISD::SETLE  || CC == ISD::SETLT)
     swpCmpOps = true;
----------------
Ditto.


================
Comment at: lib/Target/ARM/ARMISelLowering.cpp:4216
   // unordered case.
   if (CC == ISD::SETUNE || CC == ISD::SETNE) {
     CondCode = ARMCC::EQ;
----------------
Ditto.


================
Comment at: lib/Target/ARM/ARMISelLowering.cpp:13709
     const unsigned SrcSz = VecVT.getVectorElementType().getSizeInBits();
     (void)SrcSz;
     assert(SrcSz == Known.getBitWidth());
----------------
?


================
Comment at: lib/Target/SystemZ/SystemZISelLowering.cpp:3742
 }
 
 SDValue SystemZTargetLowering::lowerSTACKSAVE(SDValue Op,
----------------
Ditto.


================
Comment at: lib/Target/SystemZ/SystemZISelLowering.h:646
 
   MachineMemOperand::Flags getMMOFlags(const Instruction &I) const override;
   const TargetRegisterClass *getRepRegClassFor(MVT VT) const override;
----------------
Should this be in another patch?


================
Comment at: lib/Target/X86/X86ISelLowering.cpp:6909
   }
 
   // Actual nodes that may contain scalar elements
----------------
Ditto.


================
Comment at: lib/Target/X86/X86ISelLowering.cpp:7479
         if (SDValue RepeatLoad = EltsFromConsecutiveLoads(
                 RepeatVT, RepeatedLoads, DL, DAG, Subtarget, isAfterLegalize)) {
           unsigned Opcode = RepeatSize > ScalarSize ? X86ISD::SUBV_BROADCAST
----------------
Ditto.


================
Comment at: lib/Target/X86/X86ISelLowering.cpp:7510
                                   isAfterLegalize);
 }
 
----------------
Ditto.


================
Comment at: lib/Target/X86/X86ISelLowering.cpp:28873
   }
 
   // Transfer the remainder of ThisMBB and its successor edges to SinkMBB.
----------------
Ditto.


================
Comment at: lib/Target/X86/X86ISelLowering.cpp:32820
   // Attempt to combine into a vector load/broadcast.
   if (SDValue LD = combineToConsecutiveLoads(VT, N, dl, DAG, Subtarget, true))
     return LD;
----------------
Ditto.


================
Comment at: lib/Target/X86/X86ISelLowering.cpp:41950
 }
 
 static SDValue combineInsertSubvector(SDNode *N, SelectionDAG &DAG,
----------------
Ditto.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D58690/new/

https://reviews.llvm.org/D58690