[PATCH] D59174: [DAGCombine][AArch64] Fold (x & ~y) | y patterns

[Nikita Popov via Phabricator via llvm-commits]

nikic marked 2 inline comments as done.
nikic added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:6927
+  if (ISD::isBuildVectorAllOnes(BVN))
+    return LHS;
+
----------------
nikic wrote:
> An alternative and probably better solution would be to delay BIC formation until after legalization (at least vec op legalization), so there is more opportunity for generic combines to apply first. Is there a way to know in here which legalization stage we are currently in and would it be okay to check it?
I've opened D59187 for this variant.


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Comment at: llvm/test/CodeGen/AArch64/sat-add.ll:607
 ; CHECK-NEXT:    cmhi v0.8h, v0.8h, v2.8h
 ; CHECK-NEXT:    bic v1.16b, v1.16b, v0.16b
 ; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b
----------------
nikic wrote:
> There's still some redundant bic's left here. The reason is that isBitwiseNot (and the whole isConstOrConstSplat functionality) does not support build vector constants. Handling this in isBitwiseNot is possible (and apparently only affects this test across all targets), but I think the more robust solution would be to migrate the whole isConstOrConstSplat functionality to return APInt and support implicit build vector truncation.
I've opened https://bugs.llvm.org/show_bug.cgi?id=41020 to keep track of this.


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D59174/new/

https://reviews.llvm.org/D59174