[llvm] r355753 - [RISCV] Allow access to FP CSRs without F extension
Ana Pazos via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 8 15:01:08 PST 2019
Author: apazos
Date: Fri Mar 8 15:01:08 2019
New Revision: 355753
URL: http://llvm.org/viewvc/llvm-project?rev=355753&view=rev
Log:
[RISCV] Allow access to FP CSRs without F extension
Summary:
Floating-point CSRs should be accessible even when F extension is not enabled.
But pseudo instructions that access floating point CSRs still require the F extension.
GNU tools already implement this behavior. RISC-V spec is pending update to reflect
this behavior and to extend it to pseudo instructions that access floating point CSRs.
Reviewers: asb
Reviewed By: asb
Subscribers: asb, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, llvm-commits
Differential Revision: https://reviews.llvm.org/D58932
Modified:
llvm/trunk/lib/Target/RISCV/RISCVSystemOperands.td
llvm/trunk/test/MC/RISCV/csr-aliases.s
llvm/trunk/test/MC/RISCV/rv32i-valid.s
llvm/trunk/test/MC/RISCV/rvf-user-csr-names.s
llvm/trunk/test/MC/RISCV/user-csr-names-invalid.s
Modified: llvm/trunk/lib/Target/RISCV/RISCVSystemOperands.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVSystemOperands.td?rev=355753&r1=355752&r2=355753&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVSystemOperands.td (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVSystemOperands.td Fri Mar 8 15:01:08 2019
@@ -71,11 +71,9 @@ def : SysReg<"uip", 0x044>;
// User Floating-Point CSRs
//===--------------------------
-let FeaturesRequired = [{ {RISCV::FeatureStdExtF} }] in {
def : SysReg<"fflags", 0x001>;
def : SysReg<"frm", 0x002>;
def : SysReg<"fcsr", 0x003>;
-}
//===--------------------------
// User Counter/Timers
Modified: llvm/trunk/test/MC/RISCV/csr-aliases.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/RISCV/csr-aliases.s?rev=355753&r1=355752&r2=355753&view=diff
==============================================================================
--- llvm/trunk/test/MC/RISCV/csr-aliases.s (original)
+++ llvm/trunk/test/MC/RISCV/csr-aliases.s Fri Mar 8 15:01:08 2019
@@ -40,78 +40,78 @@
# CHECK-INST: csrrs t0, fcsr, zero
# CHECK-ALIAS: frcsr t0
# CHECK-EXT-F: frcsr t0
-# CHECK-EXT-F-OFF: csrr t0, 3
+# CHECK-EXT-F-OFF: csrr t0, fcsr
csrrs t0, 3, zero
# CHECK-INST: csrrw t1, fcsr, t2
# CHECK-ALIAS: fscsr t1, t2
# CHECK-EXT-F-ON: fscsr t1, t2
-# CHECK-EXT-F-OFF: csrrw t1, 3, t2
+# CHECK-EXT-F-OFF: csrrw t1, fcsr, t2
csrrw t1, 3, t2
# CHECK-INST: csrrw zero, fcsr, t2
# CHECK-ALIAS: fscsr t2
# CHECK-EXT-F-ON: fscsr t2
-# CHECK-EXT-F-OFF: csrw 3, t2
+# CHECK-EXT-F-OFF: csrw fcsr, t2
csrrw zero, 3, t2
# CHECK-INST: csrrw zero, fcsr, t2
# CHECK-ALIAS: fscsr t2
# CHECK-EXT-F-ON: fscsr t2
-# CHECK-EXT-F-OFF: csrw 3, t2
+# CHECK-EXT-F-OFF: csrw fcsr, t2
csrrw zero, 3, t2
# CHECK-INST: csrrw t0, frm, zero
# CHECK-ALIAS: fsrm t0, zero
# CHECK-EXT-F-ON: fsrm t0, zero
-# CHECK-EXT-F-OFF: csrrw t0, 2, zero
+# CHECK-EXT-F-OFF: csrrw t0, frm
csrrw t0, 2, zero
# CHECK-INST: csrrw t0, frm, t1
# CHECK-ALIAS: fsrm t0, t1
# CHECK-EXT-F-ON: fsrm t0, t1
-# CHECK-EXT-F-OFF: csrrw t0, 2, t1
+# CHECK-EXT-F-OFF: csrrw t0, frm, t1
csrrw t0, 2, t1
# CHECK-INST: csrrwi t0, frm, 31
# CHECK-ALIAS: fsrmi t0, 31
# CHECK-EXT-F-ON: fsrmi t0, 31
-# CHECK-EXT-F-OFF: csrrwi t0, 2, 31
+# CHECK-EXT-F-OFF: csrrwi t0, frm, 31
csrrwi t0, 2, 31
# CHECK-INST: csrrwi zero, frm, 31
# CHECK-ALIAS: fsrmi 31
# CHECK-EXT-F-ON: fsrmi 31
-# CHECK-EXT-F-OFF: csrwi 2, 31
+# CHECK-EXT-F-OFF: csrwi frm, 31
csrrwi zero, 2, 31
# CHECK-INST: csrrs t0, fflags, zero
# CHECK-ALIAS: frflags t0
# CHECK-EXT-F-ON: frflags t0
-# CHECK-EXT-F-OFF: csrr t0, 1
+# CHECK-EXT-F-OFF: csrr t0, fflags
csrrs t0, 1, zero
# CHECK-INST: csrrw t0, fflags, t2
# CHECK-ALIAS: fsflags t0, t2
# CHECK-EXT-F-ON: fsflags t0, t2
-# CHECK-EXT-F-OFF: csrrw t0, 1, t2
+# CHECK-EXT-F-OFF: csrrw t0, fflags, t2
csrrw t0, 1, t2
# CHECK-INST: csrrw zero, fflags, t2
# CHECK-ALIAS: fsflags t2
# CHECK-EXT-F-ON: fsflags t2
-# CHECK-EXT-F-OFF: csrw 1, t2
+# CHECK-EXT-F-OFF: csrw fflags, t2
csrrw zero, 1, t2
# CHECK-INST: csrrwi t0, fflags, 31
# CHECK-ALIAS: fsflagsi t0, 31
# CHECK-EXT-F: fsflagsi t0, 31
-# CHECK-EXT-F-OFF: csrrwi t0, 1, 31
+# CHECK-EXT-F-OFF: csrrwi t0, fflags, 31
csrrwi t0, 1, 31
# CHECK-INST: csrrwi zero, fflags, 31
# CHECK-ALIAS: fsflagsi 31
# CHECK-EXT-F: fsflagsi 31
-# CHECK-EXT-F-OFF: csrwi 1, 31
+# CHECK-EXT-F-OFF: csrwi fflags, 31
csrrwi zero, 1, 31
Modified: llvm/trunk/test/MC/RISCV/rv32i-valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/RISCV/rv32i-valid.s?rev=355753&r1=355752&r2=355753&view=diff
==============================================================================
--- llvm/trunk/test/MC/RISCV/rv32i-valid.s (original)
+++ llvm/trunk/test/MC/RISCV/rv32i-valid.s Fri Mar 8 15:01:08 2019
@@ -292,7 +292,7 @@ csrrw t0, 0xfff, t1
# CHECK-ASM-AND-OBJ: csrrs s0, cycle, zero
# CHECK-ASM: encoding: [0x73,0x24,0x00,0xc0]
csrrs s0, 0xc00, x0
-# CHECK-ASM-AND-OBJ: csrrs s3, 1, s5
+# CHECK-ASM-AND-OBJ: csrrs s3, fflags, s5
# CHECK-ASM: encoding: [0xf3,0xa9,0x1a,0x00]
csrrs s3, 0x001, s5
# CHECK-ASM-AND-OBJ: csrrc sp, ustatus, ra
Modified: llvm/trunk/test/MC/RISCV/rvf-user-csr-names.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/RISCV/rvf-user-csr-names.s?rev=355753&r1=355752&r2=355753&view=diff
==============================================================================
--- llvm/trunk/test/MC/RISCV/rvf-user-csr-names.s (original)
+++ llvm/trunk/test/MC/RISCV/rvf-user-csr-names.s Fri Mar 8 15:01:08 2019
@@ -25,12 +25,12 @@
# CHECK-INST: csrrs t1, fflags, zero
# CHECK-ENC: encoding: [0x73,0x23,0x10,0x00]
# CHECK-INST-ALIAS: frflags t1
-# CHECK-INST-ALIAS-NO-F: csrr t1, 1
+# CHECK-INST-ALIAS-NO-F: csrr t1, fflags
# uimm12
# CHECK-INST: csrrs t2, fflags, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x00]
# CHECK-INST-ALIAS: frflags t2
-# CHECK-INST-ALIAS-NO-F: csrr t2, 1
+# CHECK-INST-ALIAS-NO-F: csrr t2, fflags
# name
csrrs t1, fflags, zero
# uimm12
@@ -41,12 +41,12 @@ csrrs t2, 0x001, zero
# CHECK-INST: csrrs t1, frm, zero
# CHECK-ENC: encoding: [0x73,0x23,0x20,0x00]
# CHECK-INST-ALIAS: frrm t1
-# CHECK-INST-ALIAS-NO-F: csrr t1, 2
+# CHECK-INST-ALIAS-NO-F: csrr t1, frm
# uimm12
# CHECK-INST: csrrs t2, frm, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x00]
# CHECK-INST-ALIAS: frrm t2
-# CHECK-INST-ALIAS-NO-F: csrr t2, 2
+# CHECK-INST-ALIAS-NO-F: csrr t2, frm
# name
csrrs t1, frm, zero
# uimm12
@@ -57,12 +57,12 @@ csrrs t2, 0x002, zero
# CHECK-INST: csrrs t1, fcsr, zero
# CHECK-ENC: encoding: [0x73,0x23,0x30,0x00]
# CHECK-INST-ALIAS: frcsr t1
-# CHECK-INST-ALIAS-NO-F: csrr t1, 3
+# CHECK-INST-ALIAS-NO-F: csrr t1, fcsr
# uimm12
# CHECK-INST: csrrs t2, fcsr, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x30,0x00]
# CHECK-INST-ALIAS: frcsr t2
-# CHECK-INST-ALIAS-NO-F: csrr t2, 3
+# CHECK-INST-ALIAS-NO-F: csrr t2, fcsr
# name
csrrs t1, fcsr, zero
# uimm12
Modified: llvm/trunk/test/MC/RISCV/user-csr-names-invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/RISCV/user-csr-names-invalid.s?rev=355753&r1=355752&r2=355753&view=diff
==============================================================================
--- llvm/trunk/test/MC/RISCV/user-csr-names-invalid.s (original)
+++ llvm/trunk/test/MC/RISCV/user-csr-names-invalid.s Fri Mar 8 15:01:08 2019
@@ -1,7 +1,5 @@
-# RUN: not llvm-mc -triple riscv32 < %s 2>&1 \
-# RUN: | FileCheck -check-prefix=CHECK-NEED-F %s
# RUN: not llvm-mc -triple riscv64 < %s 2>&1 \
-# RUN: | FileCheck -check-prefixes=CHECK-NEED-RV32,CHECK-NEED-F %s
+# RUN: | FileCheck -check-prefixes=CHECK-NEED-RV32 %s
# These user mode CSR register names are RV32 only.
@@ -38,10 +36,3 @@ csrrs t1, hpmcounter28h, zero # CHECK-NE
csrrs t1, hpmcounter29h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
csrrs t1, hpmcounter30h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
csrrs t1, hpmcounter31h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
-
-# These user mode CSR register names require F extension.
-
-csrrs t1, fflags, zero # CHECK-NEED-F: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, frm, zero # CHECK-NEED-F: :[[@LINE]]:11: error: system register use requires an option to be enabled
-csrrs t1, fcsr, zero # CHECK-NEED-F: :[[@LINE]]:11: error: system register use requires an option to be enabled
-
More information about the llvm-commits
mailing list