[PATCH] D58857: [HWASan] Save + print registers when tag mismatch occurs in AArch64.

Fri Mar 8 11:08:51 PST 2019

pcc added inline comments.

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Comment at: compiler-rt/lib/hwasan/hwasan_report.cc:452
+    Printf("    x%d%s%016llx", i, (i < 10) ? kDoubleSpace : kSingleSpace,
+           frame[28 - i]);
+    Printf("  x%d%s%016llx", i + 1, (i + 1 < 10) ? kDoubleSpace : kSingleSpace,
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hctim wrote:
> pcc wrote:
> > hctim wrote:
> > > pcc wrote:
> > > > The math here seems a little hard to reason about. Would it be better to store the registers in numerical order so that e.g. x0 is in frame[0], x1 is in frame[1] and so on?
> > > Have changed to do ordering for `x2` - `x28`, but as `x0`, `x1`, `x29`, and `x30` are saved in `__hwasan_check` they'll have to stay a bit out-of-order.
> > Not necessarily. I think you could do this in `__hwasan_check_*`:
> > ```
> > stp x0, x1, [sp, #-248]!
> > stp x29, x30, [sp, #232]
> > ```
> > Now all of your stores in `__hwasan_tag_mismatch` can look like this:
> > ```
> > stp xN, xN+1, [sp, #(N * 8)]
> > ```
> Done, except for a minor change to ensure that the stack pointer is 16-byte aligned (see ARM [[ http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055b/IHI0055B_aapcs64.pdf | procedure call standard ]] Sec 5.2.2.1.)
Thanks, makes sense.

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Comment at: llvm/test/CodeGen/AArch64/hwasan-check-memaccess.ll:46
 ; CHECK-NEXT: .Ltmp0:
+; CHECK-NEXT: stp x29, x30, [sp, #-16]!
+; CHECK-NEXT: stp x0, x1, [sp, #-16]!
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I think this test case needs to be updated. Same below.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D58857/new/

https://reviews.llvm.org/D58857