[PATCH] D58521: [DAGCombiner] allow truncation of binops after legalization if desirable

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added a comment.

In D58521#1406128 <https://reviews.llvm.org/D58521#1406128>, @arsenm wrote:

> IIRC the idot patterns are looking for very specific patterns and avoiding commuting to save compile time, so maybe those just need to be updated?


They can be updated, but with the patch these tests produced considerably more code.



================
Comment at: llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll:239
+; VI-NEXT:    v_add_u32_sdwa v0, vcc, v0, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+; VI-NEXT:    v_or_b32_e64 v1, s1, 4
+; VI-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
----------------
In fact this is regression as well. A scalar operation (s_) is preferable over vector (v_).


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https://reviews.llvm.org/D58521