[llvm] r355524 - [Hexagon] Avoid creating 5-instruction packets with vgather pseudos

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Wed Mar  6 09:43:50 2019
New Revision: 355524

URL: http://llvm.org/viewvc/llvm-project?rev=355524&view=rev
Log:
[Hexagon] Avoid creating 5-instruction packets with vgather pseudos

Change the resource usage of the vgather pseudos from SLOT0+LD to
SLOT0+SLOT1.

Added:
    llvm/trunk/test/CodeGen/Hexagon/packetize-vgather-slot01.mir
Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonIICHVX.td

Modified: llvm/trunk/lib/Target/Hexagon/HexagonIICHVX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonIICHVX.td?rev=355524&r1=355523&r2=355524&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonIICHVX.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonIICHVX.td Wed Mar  6 09:43:50 2019
@@ -16,12 +16,14 @@ class HVXItin {
        InstrStage<1, [CVI_XLANE,CVI_SHIFT, CVI_MPY0, CVI_MPY1]>],
       [9, 7, 7, 7], [HVX_FWD, HVX_FWD, HVX_FWD]>,
 
-    // Used by Gather Pseudo Instructions which are expanded into
-    // V6_vgather* and V6_vS32b_new_ai. Even though these instructions
-    // use CVI_ST resource, it's not included below to avoid having more than
-    // 4 InstrStages and thus changing 'MaxResTerms' to 5.
+    // Used by gather pseudo-instructions which are expanded into V6_vgather*
+    // and V6_vS32b_new_ai. Even though these instructions use CVI_LD resource,
+    // it's not included below to avoid having more than 4 InstrStages and
+    // thus changing 'MaxResTerms' to 5. Instead, both SLOT0 and SLOT1 are
+    // used, which should be sufficient.
     InstrItinData <CVI_GATHER_PSEUDO,
       [InstrStage<1, [SLOT0], 0>,
-       InstrStage<1, [CVI_LD], 0>, InstrStage<1, [CVI_ST], 0>,
+       InstrStage<1, [SLOT1], 0>,
+       InstrStage<1, [CVI_ST], 0>,
        InstrStage<1, [CVI_MPY01, CVI_XLSHF]>]>];
 }

Added: llvm/trunk/test/CodeGen/Hexagon/packetize-vgather-slot01.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/packetize-vgather-slot01.mir?rev=355524&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/packetize-vgather-slot01.mir (added)
+++ llvm/trunk/test/CodeGen/Hexagon/packetize-vgather-slot01.mir Wed Mar  6 09:43:50 2019
@@ -0,0 +1,22 @@
+# RUN: llc -march=hexagon -mcpu=hexagonv65 -mattr=+hvxv65,+hvx-length64b -run-pass=hexagon-packetizer -o - %s | FileCheck %s
+
+# Check that we don't generate a packet with 5 instructions.
+
+# CHECK: BUNDLE
+# CHECK-NEXT: V6_vaslw_acc
+# CHECK-NEXT: V6_vgathermw
+# CHECK-NEXT: V6_vS32b_new_ai
+# CHECK-NEXT: A2_addi
+# CHECK-NEXT: }
+
+name: fred
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $r0, $r1, $r2, $r3, $m0, $v0, $v1, $v2
+    $v0 = V6_vaslw_acc $v0, killed $v1, $r0
+    V6_vgathermw_pseudo $r1, $r2, $m0, killed $v2
+    $r4 = A2_addi $r1, 512
+    $r5 = A2_addi $r1, 640
+    V6_vgathermw_pseudo killed $r3, $r2, $m0, killed $v0
+...