[PATCH] D58905: [AMDGPU] Use three- and five-dword result type in image ops

[Tim Renouf via Phabricator via llvm-commits]

tpr created this revision.
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Some image ops return three or five dwords.  Previously, we modeled that
with a 4 or 8 dword register class.  The register allocator could
cleverly spot that some subregs were dead and allocate something else
there, but that caused the de-optimization that waitcnt insertion would
think that the result was used immediately.

This commit allows such an image op to have a result with a three or
five dword result, avoiding the above de-optimization.

Change-Id: I3651211bbd7ed22721ee7b9fefd7bcc60a809d8b


Repository:
  rL LLVM

https://reviews.llvm.org/D58905

Files:
  lib/Target/AMDGPU/MIMGInstructions.td
  lib/Target/AMDGPU/SIISelLowering.cpp
  test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll

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