[PATCH] D58015: [SelectionDAG][AArch64] Legalize VECREDUCE

[Amara Emerson via Phabricator via llvm-commits]

aemerson added a comment.

What about expanding the reductions into shuffle vector sequences? If we add support for that, such that the resulting constructed SDAG would be the same as the IR expansion shuffle vector sequence, then we pave the way for a move to using the intrinsics for all targets as the canonical form. So what we'd do is:

1. Add the expansion to shuffle vector sequences (instead of a naive implementation)
2. Move targets to use the intrinsic representation unconditionally. This means we don't need the useReductionIntrinsic TTI took any more. Targets' TargetLowering would need to specify which reduction kinds to expand using the new SDAG expansion code.
3. ...and as a result we can kill the ExpandReductions pass and finally move these intrinsics from experimental to fully supported and preferred representations.

I'm not saying this all needs to be done by you, but I think it's worth tackling 1) here.


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https://reviews.llvm.org/D58015