[llvm] r355178 - [MIPS GlobalISel] Fix mul operands
Vlad Tsyrklevich via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 1 10:58:00 PST 2019
This change was causing ASan failures
<http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/30018>
on the sanitizer bots, I reverted it in r355219.
FAIL: LLVM :: CodeGen/Mips/GlobalISel/instruction-select/select.mir
(10600 of 30028)
******************** TEST 'LLVM ::
CodeGen/Mips/GlobalISel/instruction-select/select.mir' FAILED
********************
Script:
--
: 'RUN: at line 2';
/b/sanitizer-x86_64-linux-fast/build/llvm_build_asan/bin/llc -O0
-mtriple=mipsel-linux-gnu -run-pass=instruction-select
-verify-machineinstrs
/b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/select.mir
-o - | /b/sanitizer-x86_64-linux-fast/build/llvm_build_asan/bin/FileCheck
/b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/select.mir
-check-prefixes=MIPS32
--
Exit Code: 2
Command Output (stderr):
--
=================================================================
==34295==ERROR: AddressSanitizer: use-after-poison on address
0x62100000e640 at pc 0x00000234d965 bp 0x7ffc4a0c1e90 sp
0x7ffc4a0c1e88
READ of size 8 at 0x62100000e640 thread T0
#0 0x234d964 in getOpcode
/b/sanitizer-x86_64-linux-fast/build/llvm/include/llvm/CodeGen/MachineInstr.h:408:39
#1 0x234d964 in (anonymous
namespace)::MipsInstructionSelector::select(llvm::MachineInstr&,
llvm::CodeGenCoverage&) const
/b/sanitizer-x86_64-linux-fast/build/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
#2 0x661fd15 in
llvm::InstructionSelect::runOnMachineFunction(llvm::MachineFunction&)
/b/sanitizer-x86_64-linux-fast/build/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp:129:18
#3 0x40dc1ba in
llvm::MachineFunctionPass::runOnFunction(llvm::Function&)
/b/sanitizer-x86_64-linux-fast/build/llvm/lib/CodeGen/MachineFunctionPass.cpp:73:13
#4 0x4b55011 in
llvm::FPPassManager::runOnFunction(llvm::Function&)
/b/sanitizer-x86_64-linux-fast/build/llvm/lib/IR/LegacyPassManager.cpp:1643:27
#5 0x4b55732 in llvm::FPPassManager::runOnModule(llvm::Module&)
/b/sanitizer-x86_64-linux-fast/build/llvm/lib/IR/LegacyPassManager.cpp:1678:16
#6 0x4b56505 in runOnModule
/b/sanitizer-x86_64-linux-fast/build/llvm/lib/IR/LegacyPassManager.cpp:1743:27
#7 0x4b56505 in llvm::legacy::PassManagerImpl::run(llvm::Module&)
/b/sanitizer-x86_64-linux-fast/build/llvm/lib/IR/LegacyPassManager.cpp:1856
#8 0xa200f9 in compileModule(char**, llvm::LLVMContext&)
/b/sanitizer-x86_64-linux-fast/build/llvm/tools/llc/llc.cpp:596:8
#9 0xa19c80 in main
/b/sanitizer-x86_64-linux-fast/build/llvm/tools/llc/llc.cpp:350:22
#10 0x7f4e60b6d2e0 in __libc_start_main
(/lib/x86_64-linux-gnu/libc.so.6+0x202e0)
#11 0x90bff9 in _start
(/b/sanitizer-x86_64-linux-fast/build/llvm_build_asan/bin/llc+0x90bff9)
0x62100000e640 is located 2368 bytes inside of 4096-byte region
[0x62100000dd00,0x62100000ed00)
allocated by thread T0 here:
#0 0x9d821f in malloc
/b/sanitizer-x86_64-linux-fast/build/llvm/projects/compiler-rt/lib/asan/asan_malloc_linux.cc:146
#1 0xa569d3 in safe_malloc
/b/sanitizer-x86_64-linux-fast/build/llvm/include/llvm/Support/MemAlloc.h:26:18
#2 0xa569d3 in Allocate
/b/sanitizer-x86_64-linux-fast/build/llvm/include/llvm/Support/Allocator.h:99
#3 0xa569d3 in llvm::BumpPtrAllocatorImpl<llvm::MallocAllocator,
4096ul, 4096ul>::StartNewSlab()
/b/sanitizer-x86_64-linux-fast/build/llvm/include/llvm/Support/Allocator.h:400
#4 0xa56709 in llvm::BumpPtrAllocatorImpl<llvm::MallocAllocator,
4096ul, 4096ul>::Allocate(unsigned long, unsigned long)
/b/sanitizer-x86_64-linux-fast/build/llvm/include/llvm/Support/Allocator.h:260:5
#5 0x40b9b93 in operator new<llvm::MallocAllocator, 4096, 4096>
/b/sanitizer-x86_64-linux-fast/build/llvm/include/llvm/Support/Allocator.h:508:20
#6 0x40b9b93 in llvm::MachineFunction::init()
/b/sanitizer-x86_64-linux-fast/build/llvm/lib/CodeGen/MachineFunction.cpp:156
#7 0x4147cd2 in
llvm::MachineModuleInfo::getOrCreateMachineFunction(llvm::Function
const&) /b/sanitizer-x86_64-linux-fast/build/llvm/lib/CodeGen/MachineModuleInfo.cpp:280:14
#8 0x4e89036 in
llvm::MIRParserImpl::parseMachineFunction(llvm::Module&,
llvm::MachineModuleInfo&)
/b/sanitizer-x86_64-linux-fast/build/llvm/lib/CodeGen/MIRParser/MIRParser.cpp:305:29
#9 0x4e9c37d in parseMachineFunctions
/b/sanitizer-x86_64-linux-fast/build/llvm/lib/CodeGen/MIRParser/MIRParser.cpp:262:9
#10 0x4e9c37d in
llvm::MIRParser::parseMachineFunctions(llvm::Module&,
llvm::MachineModuleInfo&)
/b/sanitizer-x86_64-linux-fast/build/llvm/lib/CodeGen/MIRParser/MIRParser.cpp:899
#11 0xa1ff77 in compileModule(char**, llvm::LLVMContext&)
/b/sanitizer-x86_64-linux-fast/build/llvm/tools/llc/llc.cpp:577:16
#12 0xa19c80 in main
/b/sanitizer-x86_64-linux-fast/build/llvm/tools/llc/llc.cpp:350:22
#13 0x7f4e60b6d2e0 in __libc_start_main
(/lib/x86_64-linux-gnu/libc.so.6+0x202e0)
SUMMARY: AddressSanitizer: use-after-poison
/b/sanitizer-x86_64-linux-fast/build/llvm/include/llvm/CodeGen/MachineInstr.h:408:39
in getOpcode
Shadow bytes around the buggy address:
0x0c427fff9c70: 00 f7 00 00 00 00 00 00 00 00 00 f7 00 00 00 00
0x0c427fff9c80: 00 00 00 00 f7 00 00 00 00 00 00 00 00 00 f7 00
0x0c427fff9c90: 00 00 00 00 00 00 00 f7 00 00 00 00 00 00 00 00
0x0c427fff9ca0: 00 f7 00 00 00 00 00 00 00 00 f7 00 00 00 00 00
0x0c427fff9cb0: 00 00 00 00 f7 00 00 00 00 00 00 00 00 00 00 00
=>0x0c427fff9cc0: 00 00 00 00 00 f7 f7 f7[f7]f7 f7 f7 f7 f7 f7 f7
0x0c427fff9cd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x0c427fff9ce0: f7 00 00 00 00 00 00 00 00 00 f7 00 00 00 00 00
0x0c427fff9cf0: 00 00 00 f7 00 00 00 00 00 00 00 00 00 f7 00 00
0x0c427fff9d00: 00 00 f7 00 00 00 00 00 00 00 00 00 f7 00 00 00
0x0c427fff9d10: 00 00 00 00 00 00 00 00 00 00 00 00 00 f7 f7 f7
Shadow byte legend (one shadow byte represents 8 application bytes):
Addressable: 00
Partially addressable: 01 02 03 04 05 06 07
Heap left redzone: fa
Freed heap region: fd
Stack left redzone: f1
Stack mid redzone: f2
Stack right redzone: f3
Stack after return: f5
Stack use after scope: f8
Global redzone: f9
Global init order: f6
Poisoned by user: f7
Container overflow: fc
Array cookie: ac
Intra object redzone: bb
ASan internal: fe
Left alloca redzone: ca
Right alloca redzone: cb
Shadow gap: cc
==34295==ABORTING
FileCheck error: '-' is empty.
FileCheck command line:
/b/sanitizer-x86_64-linux-fast/build/llvm_build_asan/bin/FileCheck
/b/sanitizer-x86_64-linux-fast/build/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/select.mir
-check-prefixes=MIPS32
On Thu, Feb 28, 2019 at 11:45 PM Petar Avramovic via llvm-commits <
llvm-commits at lists.llvm.org> wrote:
> Author: petar.avramovic
> Date: Thu Feb 28 23:35:57 2019
> New Revision: 355178
>
> URL: http://llvm.org/viewvc/llvm-project?rev=355178&view=rev
> Log:
> [MIPS GlobalISel] Fix mul operands
>
> Unsigned mul high for MIPS32 is selected into two PseudoInstructions:
> PseudoMULTu and PseudoMFHI that use accumulator register class ACC64 for
> some of its operands. Registers in this class have appropriate hi and lo
> register as subregisters: $lo0 and $hi0 are subregisters of $ac0 etc.
> mul instruction implicit-defs $lo0 and $hi0 according to MipsInstrInfo.td.
> In functions where mul and PseudoMULTu are present fastRegisterAllocator
> will "run out of registers during register allocation" because
> 'calcSpillCost' for $ac0 will return spillImpossible because subregisters
> $lo0 and $hi0 of $ac0 are reserved by mul instruction above. A solution is
> to mark implicit-defs of $lo0 and $hi0 as dead in mul instruction.
>
> Differential Revision: https://reviews.llvm.org/D58715
>
> Modified:
> llvm/trunk/lib/Target/Mips/MipsInstructionSelector.cpp
> llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir
> llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir
> llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll
> llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/mul.mir
>
> Modified: llvm/trunk/lib/Target/Mips/MipsInstructionSelector.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstructionSelector.cpp?rev=355178&r1=355177&r2=355178&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsInstructionSelector.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/MipsInstructionSelector.cpp Thu Feb 28
> 23:35:57 2019
> @@ -132,6 +132,10 @@ bool MipsInstructionSelector::select(Mac
> }
>
> if (selectImpl(I, CoverageInfo)) {
> + if (I.getOpcode() == Mips::MUL) {
> + I.getOperand(3).setIsDead(true);
> + I.getOperand(4).setIsDead(true);
> + }
> return true;
> }
>
>
> Modified:
> llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir?rev=355178&r1=355177&r2=355178&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir
> (original)
> +++ llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir Thu
> Feb 28 23:35:57 2019
> @@ -3,7 +3,7 @@
> --- |
>
> define void @mul_i32(i32 %x, i32 %y) {entry: ret void}
> - define void @umul_with_overflow(i32 %lhs, i32 %rhs, i1* %pcarry_flag) {
> ret void }
> + define void @umul_with_overflow(i32 %lhs, i32 %rhs, i32* %pmul, i1*
> %pcarry_flag) { ret void }
>
> ...
> ---
> @@ -20,7 +20,7 @@ body: |
> ; MIPS32: liveins: $a0, $a1
> ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
> ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
> - ; MIPS32: [[MUL:%[0-9]+]]:gpr32 = MUL [[COPY]], [[COPY1]],
> implicit-def $hi0, implicit-def $lo0
> + ; MIPS32: [[MUL:%[0-9]+]]:gpr32 = MUL [[COPY]], [[COPY1]],
> implicit-def dead $hi0, implicit-def dead $lo0
> ; MIPS32: $v0 = COPY [[MUL]]
> ; MIPS32: RetRA implicit $v0
> %0:gprb(s32) = COPY $a0
> @@ -38,13 +38,15 @@ regBankSelected: true
> tracksRegLiveness: true
> body: |
> bb.1 (%ir-block.0):
> - liveins: $a0, $a1, $a2
> + liveins: $a0, $a1, $a2, $a3
>
> ; MIPS32-LABEL: name: umul_with_overflow
> - ; MIPS32: liveins: $a0, $a1, $a2
> + ; MIPS32: liveins: $a0, $a1, $a2, $a3
> ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
> ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
> ; MIPS32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
> + ; MIPS32: [[COPY3:%[0-9]+]]:gpr32 = COPY $a3
> + ; MIPS32: [[MUL:%[0-9]+]]:gpr32 = MUL [[COPY]], [[COPY1]],
> implicit-def dead $hi0, implicit-def dead $lo0
> ; MIPS32: [[PseudoMULTu:%[0-9]+]]:acc64 = PseudoMULTu [[COPY]],
> [[COPY1]]
> ; MIPS32: [[PseudoMFHI:%[0-9]+]]:gpr32 = PseudoMFHI [[PseudoMULTu]]
> ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 0
> @@ -54,18 +56,22 @@ body: |
> ; MIPS32: [[LUi1:%[0-9]+]]:gpr32 = LUi 0
> ; MIPS32: [[ORi1:%[0-9]+]]:gpr32 = ORi [[LUi1]], 1
> ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[SLTu]], [[ORi1]]
> - ; MIPS32: SB [[AND]], [[COPY2]], 0 :: (store 1 into %ir.pcarry_flag)
> + ; MIPS32: SB [[AND]], [[COPY3]], 0 :: (store 1 into %ir.pcarry_flag)
> + ; MIPS32: SW [[MUL]], [[COPY2]], 0 :: (store 4 into %ir.pmul)
> ; MIPS32: RetRA
> %0:gprb(s32) = COPY $a0
> %1:gprb(s32) = COPY $a1
> %2:gprb(p0) = COPY $a2
> - %6:gprb(s32) = G_UMULH %0, %1
> - %7:gprb(s32) = G_CONSTANT i32 0
> - %8:gprb(s32) = G_ICMP intpred(ne), %6(s32), %7
> - %9:gprb(s32) = G_CONSTANT i32 1
> - %10:gprb(s32) = COPY %8(s32)
> - %5:gprb(s32) = G_AND %10, %9
> - G_STORE %5(s32), %2(p0) :: (store 1 into %ir.pcarry_flag)
> + %3:gprb(p0) = COPY $a3
> + %4:gprb(s32) = G_MUL %0, %1
> + %7:gprb(s32) = G_UMULH %0, %1
> + %8:gprb(s32) = G_CONSTANT i32 0
> + %9:gprb(s32) = G_ICMP intpred(ne), %7(s32), %8
> + %10:gprb(s32) = G_CONSTANT i32 1
> + %11:gprb(s32) = COPY %9(s32)
> + %6:gprb(s32) = G_AND %11, %10
> + G_STORE %6(s32), %3(p0) :: (store 1 into %ir.pcarry_flag)
> + G_STORE %4(s32), %2(p0) :: (store 4 into %ir.pmul)
> RetRA
>
> ...
>
> Modified: llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir?rev=355178&r1=355177&r2=355178&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir (original)
> +++ llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir Thu Feb 28
> 23:35:57 2019
> @@ -9,7 +9,7 @@
> define void @mul_i16_sext() {entry: ret void}
> define void @mul_i16_zext() {entry: ret void}
> define void @mul_i16_aext() {entry: ret void}
> - define void @umul_with_overflow(i32 %lhs, i32 %rhs, i1* %pcarry_flag) {
> ret void }
> + define void @umul_with_overflow(i32 %lhs, i32 %rhs, i32* %pmul, i1*
> %pcarry_flag) { ret void }
>
> ...
> ---
> @@ -218,26 +218,31 @@ alignment: 2
> tracksRegLiveness: true
> body: |
> bb.1 (%ir-block.0):
> - liveins: $a0, $a1, $a2
> + liveins: $a0, $a1, $a2, $a3
>
> ; MIPS32-LABEL: name: umul_with_overflow
> - ; MIPS32: liveins: $a0, $a1, $a2
> + ; MIPS32: liveins: $a0, $a1, $a2, $a3
> ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
> ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
> ; MIPS32: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
> + ; MIPS32: [[COPY3:%[0-9]+]]:_(p0) = COPY $a3
> + ; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY1]]
> ; MIPS32: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[COPY]], [[COPY1]]
> ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
> ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne),
> [[UMULH]](s32), [[C]]
> ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
> - ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
> - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
> - ; MIPS32: G_STORE [[AND]](s32), [[COPY2]](p0) :: (store 1 into
> %ir.pcarry_flag)
> + ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
> + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
> + ; MIPS32: G_STORE [[AND]](s32), [[COPY3]](p0) :: (store 1 into
> %ir.pcarry_flag)
> + ; MIPS32: G_STORE [[MUL]](s32), [[COPY2]](p0) :: (store 4 into
> %ir.pmul)
> ; MIPS32: RetRA
> %0:_(s32) = COPY $a0
> %1:_(s32) = COPY $a1
> %2:_(p0) = COPY $a2
> - %3:_(s32), %4:_(s1) = G_UMULO %0, %1
> - G_STORE %4(s1), %2(p0) :: (store 1 into %ir.pcarry_flag)
> + %3:_(p0) = COPY $a3
> + %4:_(s32), %5:_(s1) = G_UMULO %0, %1
> + G_STORE %5(s1), %3(p0) :: (store 1 into %ir.pcarry_flag)
> + G_STORE %4(s32), %2(p0) :: (store 4 into %ir.pmul)
> RetRA
>
> ...
>
> Modified: llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll?rev=355178&r1=355177&r2=355178&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll Thu Feb 28
> 23:35:57 2019
> @@ -88,9 +88,10 @@ entry:
> }
>
> declare { i32, i1 } @llvm.umul.with.overflow.i32(i32, i32)
> -define void @umul_with_overflow(i32 %lhs, i32 %rhs, i1* %pcarry_flag) {
> +define void @umul_with_overflow(i32 %lhs, i32 %rhs, i32* %pmul, i1*
> %pcarry_flag) {
> ; MIPS32-LABEL: umul_with_overflow:
> ; MIPS32: # %bb.0:
> +; MIPS32-NEXT: mul $1, $4, $5
> ; MIPS32-NEXT: multu $4, $5
> ; MIPS32-NEXT: mfhi $4
> ; MIPS32-NEXT: lui $5, 0
> @@ -100,11 +101,14 @@ define void @umul_with_overflow(i32 %lhs
> ; MIPS32-NEXT: lui $5, 0
> ; MIPS32-NEXT: ori $5, $5, 1
> ; MIPS32-NEXT: and $4, $4, $5
> -; MIPS32-NEXT: sb $4, 0($6)
> +; MIPS32-NEXT: sb $4, 0($7)
> +; MIPS32-NEXT: sw $1, 0($6)
> ; MIPS32-NEXT: jr $ra
> ; MIPS32-NEXT: nop
> %res = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %lhs, i32 %rhs)
> %carry_flag = extractvalue { i32, i1 } %res, 1
> + %mul = extractvalue { i32, i1 } %res, 0
> store i1 %carry_flag, i1* %pcarry_flag
> + store i32 %mul, i32* %pmul
> ret void
> }
>
> Modified: llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/mul.mir
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/mul.mir?rev=355178&r1=355177&r2=355178&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/mul.mir
> (original)
> +++ llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/mul.mir Thu Feb
> 28 23:35:57 2019
> @@ -3,7 +3,7 @@
> --- |
>
> define void @mul_i32(i32 %x, i32 %y) {entry: ret void}
> - define void @umul_with_overflow(i32 %lhs, i32 %rhs, i1* %pcarry_flag) {
> ret void }
> + define void @umul_with_overflow(i32 %lhs, i32 %rhs, i32* %pmul, i1*
> %pcarry_flag) { ret void }
>
> ...
> ---
> @@ -36,31 +36,37 @@ legalized: true
> tracksRegLiveness: true
> body: |
> bb.1 (%ir-block.0):
> - liveins: $a0, $a1, $a2
> + liveins: $a0, $a1, $a2, $a3
>
> ; MIPS32-LABEL: name: umul_with_overflow
> - ; MIPS32: liveins: $a0, $a1, $a2
> + ; MIPS32: liveins: $a0, $a1, $a2, $a3
> ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
> ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
> ; MIPS32: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
> + ; MIPS32: [[COPY3:%[0-9]+]]:gprb(p0) = COPY $a3
> + ; MIPS32: [[MUL:%[0-9]+]]:gprb(s32) = G_MUL [[COPY]], [[COPY1]]
> ; MIPS32: [[UMULH:%[0-9]+]]:gprb(s32) = G_UMULH [[COPY]], [[COPY1]]
> ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
> ; MIPS32: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(ne),
> [[UMULH]](s32), [[C]]
> ; MIPS32: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
> - ; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY [[ICMP]](s32)
> - ; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY3]], [[C1]]
> - ; MIPS32: G_STORE [[AND]](s32), [[COPY2]](p0) :: (store 1 into
> %ir.pcarry_flag)
> + ; MIPS32: [[COPY4:%[0-9]+]]:gprb(s32) = COPY [[ICMP]](s32)
> + ; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY4]], [[C1]]
> + ; MIPS32: G_STORE [[AND]](s32), [[COPY3]](p0) :: (store 1 into
> %ir.pcarry_flag)
> + ; MIPS32: G_STORE [[MUL]](s32), [[COPY2]](p0) :: (store 4 into
> %ir.pmul)
> ; MIPS32: RetRA
> %0:_(s32) = COPY $a0
> %1:_(s32) = COPY $a1
> %2:_(p0) = COPY $a2
> - %6:_(s32) = G_UMULH %0, %1
> - %7:_(s32) = G_CONSTANT i32 0
> - %8:_(s32) = G_ICMP intpred(ne), %6(s32), %7
> - %9:_(s32) = G_CONSTANT i32 1
> - %10:_(s32) = COPY %8(s32)
> - %5:_(s32) = G_AND %10, %9
> - G_STORE %5(s32), %2(p0) :: (store 1 into %ir.pcarry_flag)
> + %3:_(p0) = COPY $a3
> + %4:_(s32) = G_MUL %0, %1
> + %7:_(s32) = G_UMULH %0, %1
> + %8:_(s32) = G_CONSTANT i32 0
> + %9:_(s32) = G_ICMP intpred(ne), %7(s32), %8
> + %10:_(s32) = G_CONSTANT i32 1
> + %11:_(s32) = COPY %9(s32)
> + %6:_(s32) = G_AND %11, %10
> + G_STORE %6(s32), %3(p0) :: (store 1 into %ir.pcarry_flag)
> + G_STORE %4(s32), %2(p0) :: (store 4 into %ir.pmul)
> RetRA
>
> ...
>
>
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