[PATCH] D58800: [WebAssembly] Lower SIMD shifts since they are fixed in V8

[Thomas Lively via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL355163: [WebAssembly] Lower SIMD shifts since they are fixed in V8 (authored by tlively, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D58800?vs=188805&id=188825#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D58800/new/

https://reviews.llvm.org/D58800

Files:
  llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp


Index: llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
===================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -1291,11 +1291,6 @@
   // Only manually lower vector shifts
   assert(Op.getSimpleValueType().isVector());
 
-  // Expand all vector shifts until V8 fixes its implementation
-  // TODO: remove this once V8 is fixed
-  if (!Subtarget->hasUnimplementedSIMD128())
-    return unrollVectorShift(Op, DAG);
-
   // Unroll non-splat vector shifts
   BuildVectorSDNode *ShiftVec;
   SDValue SplatVal;


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