[llvm] r355101 - [Target][ARM] Add a usage for SrcSz to unbreak build-bots without assertions

[Kadir Cetinkaya via llvm-commits]

Author: kadircet
Date: Thu Feb 28 07:55:11 2019
New Revision: 355101

URL: http://llvm.org/viewvc/llvm-project?rev=355101&view=rev
Log:
[Target][ARM] Add a usage for SrcSz to unbreak build-bots without assertions

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=355101&r1=355100&r2=355101&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Feb 28 07:55:11 2019
@@ -13701,6 +13701,7 @@ void ARMTargetLowering::computeKnownBits
     EVT VT = Op.getValueType();
     const unsigned DstSz = VT.getScalarSizeInBits();
     const unsigned SrcSz = VecVT.getVectorElementType().getSizeInBits();
+    (void)SrcSz;
     assert(SrcSz == Known.getBitWidth());
     assert(DstSz > SrcSz);
     if (Op.getOpcode() == ARMISD::VGETLANEs)