[llvm] r355050 - [AArch64] Generate FP16 vector compare instructions.
Abderrazek Zaafrani via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 27 16:31:38 PST 2019
Author: az
Date: Wed Feb 27 16:31:38 2019
New Revision: 355050
URL: http://llvm.org/viewvc/llvm-project?rev=355050&view=rev
Log:
[AArch64] Generate FP16 vector compare instructions.
https://reviews.llvm.org/D58561
Modified:
llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/trunk/test/CodeGen/AArch64/fp16-v4-instructions.ll
llvm/trunk/test/CodeGen/AArch64/fp16-v8-instructions.ll
Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=355050&r1=355049&r2=355050&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Wed Feb 27 16:31:38 2019
@@ -7779,8 +7779,8 @@ SDValue AArch64TargetLowering::LowerVSET
// Make v4f16 (only) fcmp operations utilise vector instructions
// v8f16 support will be a litle more complicated
- if (LHS.getValueType().getVectorElementType() == MVT::f16) {
- if (!FullFP16 && LHS.getValueType().getVectorNumElements() == 4) {
+ if (!FullFP16 && LHS.getValueType().getVectorElementType() == MVT::f16) {
+ if (LHS.getValueType().getVectorNumElements() == 4) {
LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::v4f32, LHS);
RHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::v4f32, RHS);
SDValue NewSetcc = DAG.getSetCC(dl, MVT::v4i16, LHS, RHS, CC);
@@ -7790,8 +7790,8 @@ SDValue AArch64TargetLowering::LowerVSET
return SDValue();
}
- assert(LHS.getValueType().getVectorElementType() == MVT::f32 ||
- LHS.getValueType().getVectorElementType() == MVT::f64);
+ assert((!FullFP16 && LHS.getValueType().getVectorElementType() != MVT::f16) ||
+ LHS.getValueType().getVectorElementType() != MVT::f128);
// Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
// clean. Some of them require two branches to implement.
Modified: llvm/trunk/test/CodeGen/AArch64/fp16-v4-instructions.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/fp16-v4-instructions.ll?rev=355050&r1=355049&r2=355050&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/fp16-v4-instructions.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/fp16-v4-instructions.ll Wed Feb 27 16:31:38 2019
@@ -304,15 +304,7 @@ define <4 x i1> @test_fcmp_une(<4 x half
; CHECK-FP16-LABEL: test_fcmp_une:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, ne
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, ne
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, ne
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, ne
-; CHECK-FP16: ret
+; CHECK-FP16: fcmeq v{{[0-9]}}.4h, v{{[0-9]}}.4h
%1 = fcmp une <4 x half> %a, %b
ret <4 x i1> %1
}
@@ -330,15 +322,8 @@ define <4 x i1> @test_fcmp_ueq(<4 x half
; CHECK-FP16-LABEL: test_fcmp_ueq:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, eq
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, eq
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, eq
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, eq
-; CHECK-FP16: ret
+; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
+; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
%1 = fcmp ueq <4 x half> %a, %b
ret <4 x i1> %1
}
@@ -354,15 +339,7 @@ define <4 x i1> @test_fcmp_ugt(<4 x half
; CHECK-FP16-LABEL: test_fcmp_ugt:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, hi
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, hi
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, hi
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, hi
-; CHECK-FP16: ret
+; CHECK-FP16: fcmge v{{[0-9]}}.4h, v{{[0-9]}}.4h
%1 = fcmp ugt <4 x half> %a, %b
ret <4 x i1> %1
}
@@ -378,15 +355,7 @@ define <4 x i1> @test_fcmp_uge(<4 x half
; CHECK-FP16-LABEL: test_fcmp_uge:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, pl
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, pl
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, pl
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, pl
-; CHECK-FP16: ret
+; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
%1 = fcmp uge <4 x half> %a, %b
ret <4 x i1> %1
}
@@ -402,15 +371,7 @@ define <4 x i1> @test_fcmp_ult(<4 x half
; CHECK-FP16-LABEL: test_fcmp_ult:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, lt
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, lt
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, lt
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, lt
-; CHECK-FP16: ret
+; CHECK-FP16: fcmge v{{[0-9]}}.4h, v{{[0-9]}}.4h
%1 = fcmp ult <4 x half> %a, %b
ret <4 x i1> %1
}
@@ -426,15 +387,7 @@ define <4 x i1> @test_fcmp_ule(<4 x half
; CHECK-FP16-LABEL: test_fcmp_ule:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, le
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, le
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, le
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, le
-; CHECK-FP16: ret
+; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
%1 = fcmp ule <4 x half> %a, %b
ret <4 x i1> %1
}
@@ -452,15 +405,8 @@ define <4 x i1> @test_fcmp_uno(<4 x half
; CHECK-FP16-LABEL: test_fcmp_uno:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, vs
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, vs
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, vs
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, vs
-; CHECK-FP16: ret
+; CHECK-FP16: fcmge v{{[0-9]}}.4h, v{{[0-9]}}.4h
+; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
%1 = fcmp uno <4 x half> %a, %b
ret <4 x i1> %1
}
@@ -477,15 +423,8 @@ define <4 x i1> @test_fcmp_one(<4 x half
; CHECK-FP16-LABEL: test_fcmp_one:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, mi
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, mi
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, mi
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, mi
-; CHECK-FP16: ret
+; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
+; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
%1 = fcmp one <4 x half> %a, %b
ret <4 x i1> %1
}
@@ -500,15 +439,7 @@ define <4 x i1> @test_fcmp_oeq(<4 x half
; CHECK-FP16-LABEL: test_fcmp_oeq:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, eq
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, eq
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, eq
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, eq
-; CHECK-FP16: ret
+; CHECK-FP16: fcmeq v{{[0-9]}}.4h, v{{[0-9]}}.4h
%1 = fcmp oeq <4 x half> %a, %b
ret <4 x i1> %1
}
@@ -523,15 +454,7 @@ define <4 x i1> @test_fcmp_ogt(<4 x half
; CHECK-FP16-LABEL: test_fcmp_ogt:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, gt
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, gt
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, gt
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, gt
-; CHECK-FP16: ret
+; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
%1 = fcmp ogt <4 x half> %a, %b
ret <4 x i1> %1
}
@@ -546,15 +469,7 @@ define <4 x i1> @test_fcmp_oge(<4 x half
; CHECK-FP16-LABEL: test_fcmp_oge:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, ge
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, ge
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, ge
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, ge
-; CHECK-FP16: ret
+; CHECK-FP16: fcmge v{{[0-9]}}.4h, v{{[0-9]}}.4h
%1 = fcmp oge <4 x half> %a, %b
ret <4 x i1> %1
}
@@ -569,15 +484,7 @@ define <4 x i1> @test_fcmp_olt(<4 x half
; CHECK-FP16-LABEL: test_fcmp_olt:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, mi
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, mi
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, mi
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, mi
-; CHECK-FP16: ret
+; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
%1 = fcmp olt <4 x half> %a, %b
ret <4 x i1> %1
}
@@ -592,15 +499,7 @@ define <4 x i1> @test_fcmp_ole(<4 x half
; CHECK-FP16-LABEL: test_fcmp_ole:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, ls
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, ls
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, ls
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, ls
-; CHECK-FP16: ret
+; CHECK-FP16: fcmge v{{[0-9]}}.4h, v{{[0-9]}}.4h
%1 = fcmp ole <4 x half> %a, %b
ret <4 x i1> %1
}
@@ -617,15 +516,8 @@ define <4 x i1> @test_fcmp_ord(<4 x half
; CHECK-FP16-LABEL: test_fcmp_ord:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, vc
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, vc
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, vc
-; CHECK-FP16: fcmp h{{.}}, h{{.}}
-; CHECK-FP16: csetm {{.*}}, vc
-; CHECK-FP16: ret
+; CHECK-FP16: fcmge v{{[0-9]}}.4h, v{{[0-9]}}.4h
+; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
%1 = fcmp ord <4 x half> %a, %b
ret <4 x i1> %1
}
Modified: llvm/trunk/test/CodeGen/AArch64/fp16-v8-instructions.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/fp16-v8-instructions.ll?rev=355050&r1=355049&r2=355050&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/fp16-v8-instructions.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/fp16-v8-instructions.ll Wed Feb 27 16:31:38 2019
@@ -450,14 +450,7 @@ define <8 x i1> @test_fcmp_une(<8 x half
; CHECK-FP16-LABEL: test_fcmp_une:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG: fcmeq v{{[0-9]}}.8h, v{{[0-9]}}.8h
%1 = fcmp une <8 x half> %a, %b
ret <8 x i1> %1
@@ -468,14 +461,8 @@ define <8 x i1> @test_fcmp_ueq(<8 x half
; CHECK-FP16-LABEL: test_fcmp_ueq:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
+; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
%1 = fcmp ueq <8 x half> %a, %b
ret <8 x i1> %1
@@ -486,14 +473,7 @@ define <8 x i1> @test_fcmp_ugt(<8 x half
; CHECK-FP16-LABEL: test_fcmp_ugt:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG: fcmge v{{[0-9]}}.8h, v{{[0-9]}}.8h
%1 = fcmp ugt <8 x half> %a, %b
ret <8 x i1> %1
@@ -504,14 +484,7 @@ define <8 x i1> @test_fcmp_uge(<8 x half
; CHECK-FP16-LABEL: test_fcmp_uge:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
%1 = fcmp uge <8 x half> %a, %b
ret <8 x i1> %1
@@ -522,14 +495,7 @@ define <8 x i1> @test_fcmp_ult(<8 x half
; CHECK-FP16-LABEL: test_fcmp_ult:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG: fcmge v{{[0-9]}}.8h, v{{[0-9]}}.8h
%1 = fcmp ult <8 x half> %a, %b
ret <8 x i1> %1
@@ -540,14 +506,7 @@ define <8 x i1> @test_fcmp_ule(<8 x half
; CHECK-FP16-LABEL: test_fcmp_ule:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
%1 = fcmp ule <8 x half> %a, %b
ret <8 x i1> %1
@@ -558,14 +517,8 @@ define <8 x i1> @test_fcmp_uno(<8 x half
; CHECK-FP16-LABEL: test_fcmp_uno:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG: fcmge v{{[0-9]}}.8h, v{{[0-9]}}.8h
+; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
%1 = fcmp uno <8 x half> %a, %b
ret <8 x i1> %1
@@ -576,14 +529,8 @@ define <8 x i1> @test_fcmp_one(<8 x half
; CHECK-FP16-LABEL: test_fcmp_one:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
+; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
%1 = fcmp one <8 x half> %a, %b
ret <8 x i1> %1
@@ -594,14 +541,7 @@ define <8 x i1> @test_fcmp_oeq(<8 x half
; CHECK-FP16-LABEL: test_fcmp_oeq:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG: fcmeq v{{[0-9]}}.8h, v{{[0-9]}}.8h
%1 = fcmp oeq <8 x half> %a, %b
ret <8 x i1> %1
@@ -612,14 +552,7 @@ define <8 x i1> @test_fcmp_ogt(<8 x half
; CHECK-FP16-LABEL: test_fcmp_ogt:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
%1 = fcmp ogt <8 x half> %a, %b
ret <8 x i1> %1
@@ -630,14 +563,7 @@ define <8 x i1> @test_fcmp_oge(<8 x half
; CHECK-FP16-LABEL: test_fcmp_oge:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG: fcmge v{{[0-9]}}.8h, v{{[0-9]}}.8h
%1 = fcmp oge <8 x half> %a, %b
ret <8 x i1> %1
@@ -648,14 +574,7 @@ define <8 x i1> @test_fcmp_olt(<8 x half
; CHECK-FP16-LABEL: test_fcmp_olt:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
%1 = fcmp olt <8 x half> %a, %b
ret <8 x i1> %1
@@ -666,14 +585,7 @@ define <8 x i1> @test_fcmp_ole(<8 x half
; CHECK-FP16-LABEL: test_fcmp_ole:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG: fcmge v{{[0-9]}}.8h, v{{[0-9]}}.8h
%1 = fcmp ole <8 x half> %a, %b
ret <8 x i1> %1
@@ -684,14 +596,8 @@ define <8 x i1> @test_fcmp_ord(<8 x half
; CHECK-FP16-LABEL: test_fcmp_ord:
; CHECK-FP16-NOT: fcvt
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
-; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
+; CHECK-FP16-DAG: fcmge v{{[0-9]}}.8h, v{{[0-9]}}.8h
+; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
%1 = fcmp ord <8 x half> %a, %b
ret <8 x i1> %1
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