[PATCH] D58703: [x86] convert anyext of pinsrb scalar op to subreg insert

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a comment.

In D58703#1411623 <https://reviews.llvm.org/D58703#1411623>, @craig.topper wrote:

> I'm not convinced that the dependency logic in the frontend and the renaming portion of Intel CPUs know that this instruction only uses the lower 8 bits. Same with BT/BTC/BTR/BTS/SHLX/SHRX/SARX and probably others. On Sandy Bridge and later CPUs, probably the worst this means is that it would force an AH/BH/CH/DH merge if it had been written independently previously. Bits 63:16 and 7:0 are always together. In 64-bit mode that should never really happen since we won't consider the AH/BH/CH/DH for general use by the register allocator.


So the movzbl here and in the other patch are preferred? I’m happy to leave this as-is if everyone’s ok with the x86 diffs in D58521 <https://reviews.llvm.org/D58521>. Personally, I don’t think those tests with extra instructions are worth worrying about unless there’s some evidence of a perf regression from that.


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