[llvm] r354733 - [WebAssembly] Fix select of and (PR40805)
Hans Wennborg via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 26 02:30:34 PST 2019
Merged to release_80 in r354860.
On Sat, Feb 23, 2019 at 7:58 PM Nikita Popov via llvm-commits
<llvm-commits at lists.llvm.org> wrote:
>
> Author: nikic
> Date: Sat Feb 23 10:59:01 2019
> New Revision: 354733
>
> URL: http://llvm.org/viewvc/llvm-project?rev=354733&view=rev
> Log:
> [WebAssembly] Fix select of and (PR40805)
>
> Fixes https://bugs.llvm.org/show_bug.cgi?id=40805 introduced by
> patterns added in D53676.
>
> I'm removing the patterns entirely here, as they are not correct
> in the general case. If necessary something more specific can be
> added in the future.
>
> Differential Revision: https://reviews.llvm.org/D58575
>
> Modified:
> llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrInteger.td
> llvm/trunk/test/CodeGen/WebAssembly/select.ll
> llvm/trunk/test/CodeGen/WebAssembly/simd-select.ll
>
> Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrInteger.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrInteger.td?rev=354733&r1=354732&r2=354733&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrInteger.td (original)
> +++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrInteger.td Sat Feb 23 10:59:01 2019
> @@ -121,10 +121,3 @@ def : Pat<(select (i32 (seteq I32:$cond,
> (SELECT_I32 I32:$rhs, I32:$lhs, I32:$cond)>;
> def : Pat<(select (i32 (seteq I32:$cond, 0)), I64:$lhs, I64:$rhs),
> (SELECT_I64 I64:$rhs, I64:$lhs, I32:$cond)>;
> -
> -// The legalizer inserts an unnecessary `and 1` to make input conform
> -// to getBooleanContents, which we can lower away.
> -def : Pat<(select (i32 (and I32:$cond, 1)), I32:$lhs, I32:$rhs),
> - (SELECT_I32 I32:$lhs, I32:$rhs, I32:$cond)>;
> -def : Pat<(select (i32 (and I32:$cond, 1)), I64:$lhs, I64:$rhs),
> - (SELECT_I64 I64:$lhs, I64:$rhs, I32:$cond)>;
>
> Modified: llvm/trunk/test/CodeGen/WebAssembly/select.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/WebAssembly/select.ll?rev=354733&r1=354732&r2=354733&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/WebAssembly/select.ll (original)
> +++ llvm/trunk/test/CodeGen/WebAssembly/select.ll Sat Feb 23 10:59:01 2019
> @@ -17,8 +17,10 @@ define i32 @select_i32_bool(i1 zeroext %
>
> ; CHECK-LABEL: select_i32_bool_nozext:
> ; CHECK-NEXT: .functype select_i32_bool_nozext (i32, i32, i32) -> (i32){{$}}
> -; SLOW-NEXT: i32.select $push0=, $1, $2, $0{{$}}
> -; SLOW-NEXT: return $pop0{{$}}
> +; SLOW-NEXT: i32.const $push0=, 1{{$}}
> +; SLOW-NEXT: i32.and $push1=, $0, $pop0{{$}}
> +; SLOW-NEXT: i32.select $push2=, $1, $2, $pop1{{$}}
> +; SLOW-NEXT: return $pop2{{$}}
> define i32 @select_i32_bool_nozext(i1 %a, i32 %b, i32 %c) {
> %cond = select i1 %a, i32 %b, i32 %c
> ret i32 %cond
> @@ -55,8 +57,10 @@ define i64 @select_i64_bool(i1 zeroext %
>
> ; CHECK-LABEL: select_i64_bool_nozext:
> ; CHECK-NEXT: .functype select_i64_bool_nozext (i32, i64, i64) -> (i64){{$}}
> -; SLOW-NEXT: i64.select $push0=, $1, $2, $0{{$}}
> -; SLOW-NEXT: return $pop0{{$}}
> +; SLOW-NEXT: i32.const $push0=, 1{{$}}
> +; SLOW-NEXT: i32.and $push1=, $0, $pop0{{$}}
> +; SLOW-NEXT: i64.select $push2=, $1, $2, $pop1{{$}}
> +; SLOW-NEXT: return $pop2{{$}}
> define i64 @select_i64_bool_nozext(i1 %a, i64 %b, i64 %c) {
> %cond = select i1 %a, i64 %b, i64 %c
> ret i64 %cond
> @@ -157,3 +161,16 @@ define double @select_f64_ne(i32 %a, dou
> %cond = select i1 %cmp, double %b, double %c
> ret double %cond
> }
> +
> +; CHECK-LABEL: pr40805:
> +; CHECK-NEXT: .functype pr40805 (i32, i32, i32) -> (i32){{$}}
> +; SLOW-NEXT: i32.const $push0=, 1{{$}}
> +; SLOW-NEXT: i32.and $push1=, $0, $pop0{{$}}
> +; SLOW-NEXT: i32.select $push2=, $1, $2, $pop1{{$}}
> +; SLOW-NEXT: return $pop2{{$}}
> +define i32 @pr40805(i32 %x, i32 %y, i32 %z) {
> + %a = and i32 %x, 1
> + %b = icmp ne i32 %a, 0
> + %c = select i1 %b, i32 %y, i32 %z
> + ret i32 %c
> +}
>
> Modified: llvm/trunk/test/CodeGen/WebAssembly/simd-select.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/WebAssembly/simd-select.ll?rev=354733&r1=354732&r2=354733&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/WebAssembly/simd-select.ll (original)
> +++ llvm/trunk/test/CodeGen/WebAssembly/simd-select.ll Sat Feb 23 10:59:01 2019
> @@ -29,7 +29,7 @@ define <16 x i8> @vselect_v16i8(<16 x i1
> ; CHECK-NEXT: i8x16.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
> ; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
> ; CHECK-NEXT: return $pop[[R]]{{$}}
> -define <16 x i8> @select_v16i8(i1 %c, <16 x i8> %x, <16 x i8> %y) {
> +define <16 x i8> @select_v16i8(i1 zeroext %c, <16 x i8> %x, <16 x i8> %y) {
> %res = select i1 %c, <16 x i8> %x, <16 x i8> %y
> ret <16 x i8> %res
> }
> @@ -99,7 +99,7 @@ define <8 x i16> @vselect_v8i16(<8 x i1>
> ; CHECK-NEXT: i16x8.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
> ; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
> ; CHECK-NEXT: return $pop[[R]]{{$}}
> -define <8 x i16> @select_v8i16(i1 %c, <8 x i16> %x, <8 x i16> %y) {
> +define <8 x i16> @select_v8i16(i1 zeroext %c, <8 x i16> %x, <8 x i16> %y) {
> %res = select i1 %c, <8 x i16> %x, <8 x i16> %y
> ret <8 x i16> %res
> }
> @@ -170,7 +170,7 @@ define <4 x i32> @vselect_v4i32(<4 x i1>
> ; CHECK-NEXT: i32x4.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
> ; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
> ; CHECK-NEXT: return $pop[[R]]{{$}}
> -define <4 x i32> @select_v4i32(i1 %c, <4 x i32> %x, <4 x i32> %y) {
> +define <4 x i32> @select_v4i32(i1 zeroext %c, <4 x i32> %x, <4 x i32> %y) {
> %res = select i1 %c, <4 x i32> %x, <4 x i32> %y
> ret <4 x i32> %res
> }
> @@ -240,7 +240,7 @@ define <2 x i64> @vselect_v2i64(<2 x i1>
> ; CHECK-NEXT: i64x2.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
> ; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
> ; CHECK-NEXT: return $pop[[R]]{{$}}
> -define <2 x i64> @select_v2i64(i1 %c, <2 x i64> %x, <2 x i64> %y) {
> +define <2 x i64> @select_v2i64(i1 zeroext %c, <2 x i64> %x, <2 x i64> %y) {
> %res = select i1 %c, <2 x i64> %x, <2 x i64> %y
> ret <2 x i64> %res
> }
> @@ -313,7 +313,7 @@ define <4 x float> @vselect_v4f32(<4 x i
> ; CHECK-NEXT: i32x4.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
> ; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
> ; CHECK-NEXT: return $pop[[R]]{{$}}
> -define <4 x float> @select_v4f32(i1 %c, <4 x float> %x, <4 x float> %y) {
> +define <4 x float> @select_v4f32(i1 zeroext %c, <4 x float> %x, <4 x float> %y) {
> %res = select i1 %c, <4 x float> %x, <4 x float> %y
> ret <4 x float> %res
> }
> @@ -383,7 +383,7 @@ define <2 x double> @vselect_v2f64(<2 x
> ; CHECK-NEXT: i64x2.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
> ; CHECK-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $pop[[L3]]{{$}}
> ; CHECK-NEXT: return $pop[[R]]{{$}}
> -define <2 x double> @select_v2f64(i1 %c, <2 x double> %x, <2 x double> %y) {
> +define <2 x double> @select_v2f64(i1 zeroext %c, <2 x double> %x, <2 x double> %y) {
> %res = select i1 %c, <2 x double> %x, <2 x double> %y
> ret <2 x double> %res
> }
>
>
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