[PATCH] D58348: [AArch64] Fix for bug 35094 atomicrmw on Armv8.1-A+lse

[Christof Douma via Phabricator via llvm-commits]

christof added a comment.

In D58348#1406435 <https://reviews.llvm.org/D58348#1406435>, @efriedma wrote:

> > Is that up for debate in case this is an edge case that is unlikely to be hit?
>
> When it comes to the atomics in general, it's important to allow people to write code with the same performance characteristics as hand-written assembly, or else we force people will go around the compiler using inline asm.  But the performance impact here should be basically zero for code that doesn't use an acquire fence, I think, so it shouldn't be an issue here.


Fair enough. The loads increase the memory bus operations and in case you've got high register pressure you are using one register extra (with zero lifetime, but still). The performance impact is low. However, the programmer has asked for a load and the compiler has to proof that this cannot be observed before that load is removed, which is rather difficult when it can be used to order other memory operations.


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https://reviews.llvm.org/D58348