[PATCH] D58348: [AArch64] Fix for bug 35094 atomicrmw on Armv8.1-A+lse

[Christof Douma via Phabricator via llvm-commits]

christof added inline comments.


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Comment at: lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp:73
+// (DMB LD) once the zero register is used.
+static bool atomicReadDroppedOnZero(unsigned Opcode) {
+  switch (Opcode) {
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john.brawn wrote:
> It doesn't especially matter, as it'll already get caught by atomicBarrierDroppedOnZero, but the acquire variants of these instructions (LDADDAW etc.) also aren't counted as performing a read when the destination register is zero.
True. I'll add a remark that this is incomplete and I've left all the acquire variants to `atomicBarrierDroppedOnZero()`. If people wish to have this function complete, I can copy all the cases from atomicBarrierDroppedOnZero that apply and duplicate them here instead.

I was wondering if I cannot do this type of grouping in tablegen by leaving some label on an instruction. That way I could just test that label, rather than listing the subsets in yet another place. I'm not aware of such mechanism, unfortunately.


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  https://reviews.llvm.org/D58348/new/

https://reviews.llvm.org/D58348