[PATCH] D57888: [X86][SSE] Generalize X86ISD::BLENDI support to more value types (WIP)

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

The issue is that blendps/blendpd can be commuted to movss/movsd under optsize. This changes the number of operands. The code in TwoAddressInstructionPass tries to look for other commutable operands after making a commute in order to handle FMA3 and VPTERNLOG instructions. But the loop doesn't handle the number of operands changing.

Apparently this wasn't a problem before because FP types start with MOVSS/MOVSD due to a shuffle combine. So we leave isel with movss/movsd and two address instruction pass can commute that to blend, but won't go the other way. This increases the number of operands which isn't an issue.

To fix this I propose to use PBLENDW for the 128-bit integer case in the new isel patterns added by this patch. This keeps the blend in the integer domain and avoids the possibility of commuting to movss/movsd. I'll also fix two address instruction pass to resample the operand count after commuting to avoid this issue if there are any corner cases we haven't found yet.


Repository:
  rL LLVM

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  https://reviews.llvm.org/D57888/new/

https://reviews.llvm.org/D57888