[llvm] r354581 - [RISCV] Add implied zero offset load/store alias patterns
Alex Bradbury via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 21 06:09:35 PST 2019
Author: asb
Date: Thu Feb 21 06:09:34 2019
New Revision: 354581
URL: http://llvm.org/viewvc/llvm-project?rev=354581&view=rev
Log:
[RISCV] Add implied zero offset load/store alias patterns
Allow load/store instructions with implied zero offset for compatibility with
GNU assembler.
Differential Revision: https://reviews.llvm.org/D57141
Patch by James Clarke.
Added:
llvm/trunk/test/MC/RISCV/rv32fc-aliases-valid.s
llvm/trunk/test/MC/RISCV/rvc-aliases-valid.s
llvm/trunk/test/MC/RISCV/rvdc-aliases-valid.s
Modified:
llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td
llvm/trunk/lib/Target/RISCV/RISCVInstrInfoC.td
llvm/trunk/lib/Target/RISCV/RISCVInstrInfoD.td
llvm/trunk/lib/Target/RISCV/RISCVInstrInfoF.td
llvm/trunk/test/MC/RISCV/rv32i-aliases-valid.s
llvm/trunk/test/MC/RISCV/rv64c-aliases-valid.s
llvm/trunk/test/MC/RISCV/rv64i-aliases-valid.s
llvm/trunk/test/MC/RISCV/rvd-aliases-valid.s
llvm/trunk/test/MC/RISCV/rvf-aliases-valid.s
Modified: llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td?rev=354581&r1=354580&r2=354581&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td Thu Feb 21 06:09:34 2019
@@ -619,6 +619,24 @@ def : InstAlias<"sfence.vma", (SFENC
def : InstAlias<"sfence.vma $rs", (SFENCE_VMA GPR:$rs, X0)>;
let EmitPriority = 0 in {
+def : InstAlias<"lb $rd, (${rs1})",
+ (LB GPR:$rd, GPR:$rs1, 0)>;
+def : InstAlias<"lh $rd, (${rs1})",
+ (LH GPR:$rd, GPR:$rs1, 0)>;
+def : InstAlias<"lw $rd, (${rs1})",
+ (LW GPR:$rd, GPR:$rs1, 0)>;
+def : InstAlias<"lbu $rd, (${rs1})",
+ (LBU GPR:$rd, GPR:$rs1, 0)>;
+def : InstAlias<"lhu $rd, (${rs1})",
+ (LHU GPR:$rd, GPR:$rs1, 0)>;
+
+def : InstAlias<"sb $rs2, (${rs1})",
+ (SB GPR:$rs2, GPR:$rs1, 0)>;
+def : InstAlias<"sh $rs2, (${rs1})",
+ (SH GPR:$rs2, GPR:$rs1, 0)>;
+def : InstAlias<"sw $rs2, (${rs1})",
+ (SW GPR:$rs2, GPR:$rs1, 0)>;
+
def : InstAlias<"add $rd, $rs1, $imm12",
(ADDI GPR:$rd, GPR:$rs1, simm12:$imm12)>;
def : InstAlias<"and $rd, $rs1, $imm12",
@@ -634,6 +652,13 @@ def : InstAlias<"srl $rd, $rs1, $shamt",
def : InstAlias<"sra $rd, $rs1, $shamt",
(SRAI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt)>;
let Predicates = [IsRV64] in {
+def : InstAlias<"lwu $rd, (${rs1})",
+ (LWU GPR:$rd, GPR:$rs1, 0)>;
+def : InstAlias<"ld $rd, (${rs1})",
+ (LD GPR:$rd, GPR:$rs1, 0)>;
+def : InstAlias<"sd $rs2, (${rs1})",
+ (SD GPR:$rs2, GPR:$rs1, 0)>;
+
def : InstAlias<"addw $rd, $rs1, $imm12",
(ADDIW GPR:$rd, GPR:$rs1, simm12:$imm12)>;
def : InstAlias<"sllw $rd, $rs1, $shamt",
Modified: llvm/trunk/lib/Target/RISCV/RISCVInstrInfoC.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVInstrInfoC.td?rev=354581&r1=354580&r2=354581&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVInstrInfoC.td (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVInstrInfoC.td Thu Feb 21 06:09:34 2019
@@ -523,6 +523,56 @@ def C_UNIMP : RVInst16<(outs), (ins), "c
} // Predicates = [HasStdExtC]
//===----------------------------------------------------------------------===//
+// Assembler Pseudo Instructions
+//===----------------------------------------------------------------------===//
+
+let EmitPriority = 0 in {
+let Predicates = [HasStdExtC, HasStdExtD] in
+def : InstAlias<"c.fld $rd, (${rs1})", (C_FLD FPR64C:$rd, GPRC:$rs1, 0)>;
+
+def : InstAlias<"c.lw $rd, (${rs1})", (C_LW GPRC:$rd, GPRC:$rs1, 0)>;
+
+let Predicates = [HasStdExtC, HasStdExtF, IsRV32] in
+def : InstAlias<"c.flw $rd, (${rs1})", (C_FLW FPR32C:$rd, GPRC:$rs1, 0)>;
+
+let Predicates = [HasStdExtC, IsRV64] in
+def : InstAlias<"c.ld $rd, (${rs1})", (C_LD GPRC:$rd, GPRC:$rs1, 0)>;
+
+let Predicates = [HasStdExtC, HasStdExtD] in
+def : InstAlias<"c.fsd $rs2, (${rs1})", (C_FSD FPR64C:$rs2, GPRC:$rs1, 0)>;
+
+def : InstAlias<"c.sw $rs2, (${rs1})", (C_SW GPRC:$rs2, GPRC:$rs1, 0)>;
+
+let Predicates = [HasStdExtC, HasStdExtF, IsRV32] in
+def : InstAlias<"c.fsw $rs2, (${rs1})", (C_FSW FPR32C:$rs2, GPRC:$rs1, 0)>;
+
+let Predicates = [HasStdExtC, IsRV64] in
+def : InstAlias<"c.sd $rs2, (${rs1})", (C_SD GPRC:$rs2, GPRC:$rs1, 0)>;
+
+let Predicates = [HasStdExtC, HasStdExtD] in
+def : InstAlias<"c.fldsp $rd, (${rs1})", (C_FLDSP FPR64C:$rd, SP:$rs1, 0)>;
+
+def : InstAlias<"c.lwsp $rd, (${rs1})", (C_LWSP GPRC:$rd, SP:$rs1, 0)>;
+
+let Predicates = [HasStdExtC, HasStdExtF, IsRV32] in
+def : InstAlias<"c.flwsp $rd, (${rs1})", (C_FLWSP FPR32C:$rd, SP:$rs1, 0)>;
+
+let Predicates = [HasStdExtC, IsRV64] in
+def : InstAlias<"c.ldsp $rd, (${rs1})", (C_LDSP GPRC:$rd, SP:$rs1, 0)>;
+
+let Predicates = [HasStdExtC, HasStdExtD] in
+def : InstAlias<"c.fsdsp $rs2, (${rs1})", (C_FSDSP FPR64C:$rs2, SP:$rs1, 0)>;
+
+def : InstAlias<"c.swsp $rs2, (${rs1})", (C_SWSP GPRC:$rs2, SP:$rs1, 0)>;
+
+let Predicates = [HasStdExtC, HasStdExtF, IsRV32] in
+def : InstAlias<"c.fswsp $rs2, (${rs1})", (C_FSWSP FPR32C:$rs2, SP:$rs1, 0)>;
+
+let Predicates = [HasStdExtC, IsRV64] in
+def : InstAlias<"c.sdsp $rs2, (${rs1})", (C_SDSP GPRC:$rs2, SP:$rs1, 0)>;
+}
+
+//===----------------------------------------------------------------------===//
// Compress Instruction tablegen backend.
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/RISCV/RISCVInstrInfoD.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVInstrInfoD.td?rev=354581&r1=354580&r2=354581&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVInstrInfoD.td (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVInstrInfoD.td Thu Feb 21 06:09:34 2019
@@ -178,6 +178,9 @@ def FMV_D_X : FPUnaryOp_r<0b1111001, 0b0
//===----------------------------------------------------------------------===//
let Predicates = [HasStdExtD] in {
+def : InstAlias<"fld $rd, (${rs1})", (FLD FPR64:$rd, GPR:$rs1, 0), 0>;
+def : InstAlias<"fsd $rs2, (${rs1})", (FSD FPR64:$rs2, GPR:$rs1, 0), 0>;
+
def : InstAlias<"fmv.d $rd, $rs", (FSGNJ_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>;
def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>;
def : InstAlias<"fneg.d $rd, $rs", (FSGNJN_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>;
Modified: llvm/trunk/lib/Target/RISCV/RISCVInstrInfoF.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVInstrInfoF.td?rev=354581&r1=354580&r2=354581&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVInstrInfoF.td (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVInstrInfoF.td Thu Feb 21 06:09:34 2019
@@ -206,6 +206,9 @@ def : FPUnaryOpDynFrmAlias<FCV
//===----------------------------------------------------------------------===//
let Predicates = [HasStdExtF] in {
+def : InstAlias<"flw $rd, (${rs1})", (FLW FPR32:$rd, GPR:$rs1, 0), 0>;
+def : InstAlias<"fsw $rs2, (${rs1})", (FSW FPR32:$rs2, GPR:$rs1, 0), 0>;
+
def : InstAlias<"fmv.s $rd, $rs", (FSGNJ_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
def : InstAlias<"fabs.s $rd, $rs", (FSGNJX_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
def : InstAlias<"fneg.s $rd, $rs", (FSGNJN_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
Added: llvm/trunk/test/MC/RISCV/rv32fc-aliases-valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/RISCV/rv32fc-aliases-valid.s?rev=354581&view=auto
==============================================================================
--- llvm/trunk/test/MC/RISCV/rv32fc-aliases-valid.s (added)
+++ llvm/trunk/test/MC/RISCV/rv32fc-aliases-valid.s Thu Feb 21 06:09:34 2019
@@ -0,0 +1,14 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+c,+f -riscv-no-aliases \
+# RUN: | FileCheck -check-prefixes=CHECK-EXPAND %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+f < %s \
+# RUN: | llvm-objdump -mattr=+c,+f -riscv-no-aliases -d - \
+# RUN: | FileCheck -check-prefixes=CHECK-EXPAND %s
+
+# CHECK-EXPAND: c.flw fs0, 0(s1)
+c.flw f8, (x9)
+# CHECK-EXPAND: c.fsw fs0, 0(s1)
+c.fsw f8, (x9)
+# CHECK-EXPAND: c.flwsp fs0, 0(sp)
+c.flwsp f8, (x2)
+# CHECK-EXPAND: c.fswsp fs0, 0(sp)
+c.fswsp f8, (x2)
Modified: llvm/trunk/test/MC/RISCV/rv32i-aliases-valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/RISCV/rv32i-aliases-valid.s?rev=354581&r1=354580&r2=354581&view=diff
==============================================================================
--- llvm/trunk/test/MC/RISCV/rv32i-aliases-valid.s (original)
+++ llvm/trunk/test/MC/RISCV/rv32i-aliases-valid.s Thu Feb 21 06:09:34 2019
@@ -104,3 +104,21 @@ rdcycleh x27
# CHECK-INST: csrrs t3, timeh, zero
# CHECK-ALIAS: rdtimeh t3
rdtimeh x28
+
+# CHECK-EXPAND: lb a0, 0(a1)
+lb x10, (x11)
+# CHECK-EXPAND: lh a0, 0(a1)
+lh x10, (x11)
+# CHECK-EXPAND: lw a0, 0(a1)
+lw x10, (x11)
+# CHECK-EXPAND: lbu a0, 0(a1)
+lbu x10, (x11)
+# CHECK-EXPAND: lhu a0, 0(a1)
+lhu x10, (x11)
+
+# CHECK-EXPAND: sb a0, 0(a1)
+sb x10, (x11)
+# CHECK-EXPAND: sh a0, 0(a1)
+sh x10, (x11)
+# CHECK-EXPAND: sw a0, 0(a1)
+sw x10, (x11)
Modified: llvm/trunk/test/MC/RISCV/rv64c-aliases-valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/RISCV/rv64c-aliases-valid.s?rev=354581&r1=354580&r2=354581&view=diff
==============================================================================
--- llvm/trunk/test/MC/RISCV/rv64c-aliases-valid.s (original)
+++ llvm/trunk/test/MC/RISCV/rv64c-aliases-valid.s Thu Feb 21 06:09:34 2019
@@ -94,3 +94,12 @@ li t3, 0x700000000B00000F
li t4, 0x123456789abcdef0
# CHECK-EXPAND: c.li t5, -1
li t5, 0xFFFFFFFFFFFFFFFF
+
+# CHECK-EXPAND: c.ld s0, 0(s1)
+c.ld x8, (x9)
+# CHECK-EXPAND: c.sd s0, 0(s1)
+c.sd x8, (x9)
+# CHECK-EXPAND: c.ldsp s0, 0(sp)
+c.ldsp x8, (x2)
+# CHECK-EXPAND: c.sdsp s0, 0(sp)
+c.sdsp x8, (x2)
Modified: llvm/trunk/test/MC/RISCV/rv64i-aliases-valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/RISCV/rv64i-aliases-valid.s?rev=354581&r1=354580&r2=354581&view=diff
==============================================================================
--- llvm/trunk/test/MC/RISCV/rv64i-aliases-valid.s (original)
+++ llvm/trunk/test/MC/RISCV/rv64i-aliases-valid.s Thu Feb 21 06:09:34 2019
@@ -152,3 +152,10 @@ srlw a2,a3,4
# CHECK-INST: sraiw a2, a3, 4
# CHECK-ALIAS: sraiw a2, a3, 4
sraw a2,a3,4
+
+# CHECK-EXPAND: lwu a0, 0(a1)
+lwu x10, (x11)
+# CHECK-EXPAND: ld a0, 0(a1)
+ld x10, (x11)
+# CHECK-EXPAND: sd a0, 0(a1)
+sd x10, (x11)
Added: llvm/trunk/test/MC/RISCV/rvc-aliases-valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/RISCV/rvc-aliases-valid.s?rev=354581&view=auto
==============================================================================
--- llvm/trunk/test/MC/RISCV/rvc-aliases-valid.s (added)
+++ llvm/trunk/test/MC/RISCV/rvc-aliases-valid.s Thu Feb 21 06:09:34 2019
@@ -0,0 +1,19 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+c -riscv-no-aliases \
+# RUN: | FileCheck -check-prefixes=CHECK-EXPAND %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+c -riscv-no-aliases \
+# RUN: | FileCheck -check-prefixes=CHECK-EXPAND %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c < %s \
+# RUN: | llvm-objdump -riscv-no-aliases -d - \
+# RUN: | FileCheck -check-prefixes=CHECK-EXPAND %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+c < %s \
+# RUN: | llvm-objdump -riscv-no-aliases -d - \
+# RUN: | FileCheck -check-prefixes=CHECK-EXPAND %s
+
+# CHECK-EXPAND: c.lw s0, 0(s1)
+c.lw x8, (x9)
+# CHECK-EXPAND: c.sw s0, 0(s1)
+c.sw x8, (x9)
+# CHECK-EXPAND: c.lwsp s0, 0(sp)
+c.lwsp x8, (x2)
+# CHECK-EXPAND: c.swsp s0, 0(sp)
+c.swsp x8, (x2)
Modified: llvm/trunk/test/MC/RISCV/rvd-aliases-valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/RISCV/rvd-aliases-valid.s?rev=354581&r1=354580&r2=354581&view=diff
==============================================================================
--- llvm/trunk/test/MC/RISCV/rvd-aliases-valid.s (original)
+++ llvm/trunk/test/MC/RISCV/rvd-aliases-valid.s Thu Feb 21 06:09:34 2019
@@ -43,6 +43,13 @@ fgt.d x4, f5, f6
# CHECK-ALIAS: fle.d t2, fs1, fs0
fge.d x7, f8, f9
+# CHECK-INST: fld ft0, 0(a0)
+# CHECK-ALIAS: fld ft0, 0(a0)
+fld f0, (x10)
+# CHECK-INST: fsd ft0, 0(a0)
+# CHECK-ALIAS: fsd ft0, 0(a0)
+fsd f0, (x10)
+
##===----------------------------------------------------------------------===##
## Aliases which omit the rounding mode.
##===----------------------------------------------------------------------===##
Added: llvm/trunk/test/MC/RISCV/rvdc-aliases-valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/RISCV/rvdc-aliases-valid.s?rev=354581&view=auto
==============================================================================
--- llvm/trunk/test/MC/RISCV/rvdc-aliases-valid.s (added)
+++ llvm/trunk/test/MC/RISCV/rvdc-aliases-valid.s Thu Feb 21 06:09:34 2019
@@ -0,0 +1,18 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+c,+d -riscv-no-aliases \
+# RUN: | FileCheck -check-prefixes=CHECK-EXPAND %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+c,+d -riscv-no-aliases \
+# RUN: | FileCheck -check-prefixes=CHECK-EXPAND %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+d < %s \
+# RUN: | llvm-objdump -mattr=+c,+d -riscv-no-aliases -d - \
+# RUN: | FileCheck -check-prefixes=CHECK-EXPAND %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+c,+d < %s \
+# RUN: | llvm-objdump -mattr=+c,+d -riscv-no-aliases -d - \
+# RUN: | FileCheck -check-prefixes=CHECK-EXPAND %s
+
+c.fld f8, (x9)
+# CHECK-EXPAND: c.fsd fs0, 0(s1)
+c.fsd f8, (x9)
+# CHECK-EXPAND: c.fldsp fs0, 0(sp)
+c.fldsp f8, (x2)
+# CHECK-EXPAND: c.fsdsp fs0, 0(sp)
+c.fsdsp f8, (x2)
Modified: llvm/trunk/test/MC/RISCV/rvf-aliases-valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/RISCV/rvf-aliases-valid.s?rev=354581&r1=354580&r2=354581&view=diff
==============================================================================
--- llvm/trunk/test/MC/RISCV/rvf-aliases-valid.s (original)
+++ llvm/trunk/test/MC/RISCV/rvf-aliases-valid.s Thu Feb 21 06:09:34 2019
@@ -94,6 +94,13 @@ fmv.x.s a2, fs7
# CHECK-ALIAS: fmv.w.x ft1, a6
fmv.s.x ft1, a6
+# CHECK-INST: flw ft0, 0(a0)
+# CHECK-ALIAS: flw ft0, 0(a0)
+flw f0, (x10)
+# CHECK-INST: fsw ft0, 0(a0)
+# CHECK-ALIAS: fsw ft0, 0(a0)
+fsw f0, (x10)
+
##===----------------------------------------------------------------------===##
## Aliases which omit the rounding mode.
##===----------------------------------------------------------------------===##
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