[PATCH] D58460: [AArch64] Optimize floating point materialization

[Adhemerval Zanella via Phabricator via llvm-commits]

zatrazz created this revision.
zatrazz added reviewers: javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro, rengolin, efriedma.
zatrazz added a project: LLVM.
Herald added subscribers: mstorsjo, kristof.beyls.

This patch follows some ideas from r352866 to optimize the floating point materialization further.  It changes isFPImmLegal to considere up to 2 mov instruction. The rationale is the cost is the same for mov+fmov vs. adrp+ldr; but the mov+fmov sequence is always better because of the reduced d-cache pressure. The timings are still the same if you consider movw+movk+fmov vs. adrp+ldr will be fused (although one instruction longer).


Repository:
  rL LLVM

https://reviews.llvm.org/D58460

Files:
  lib/Target/AArch64/AArch64ISelLowering.cpp
  test/CodeGen/AArch64/arm64-fp-imm.ll
  test/CodeGen/AArch64/fpimm.ll
  test/CodeGen/AArch64/win_cst_pool.ll

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