[PATCH] D58348: [AArch64] Fix for bug 35094 atomicrmw on Armv8.1-A+lse

[Christof Douma via Phabricator via llvm-commits]

christof created this revision.
christof added reviewers: t.p.northover, john.brawn, olista01, ajasty-cavium.
Herald added subscribers: llvm-commits, jdoerfert, jfb, kristof.beyls, javed.absar.
Herald added a project: LLVM.

Fix for https://bugs.llvm.org/show_bug.cgi?id=26462

The Dead register definition pass should leave alone the atomicrmw
instructions on AArch64 (LTE extension). The reason is the following
statement in the Arm ARM:

> The ST<OP> instructions, and LD<OP> instructions where the destination
>  register is WZR or XZR, are not regarded as doing a read for the purpose
>  of a DMB LD barrier.

A good example was given in the gcc thread by Will Deacon (linked in the
bugzilla ticket):

>   P0 (atomic_int* y,atomic_int* x) {
>     atomic_store_explicit(x,1,memory_order_relaxed);
>     atomic_thread_fence(memory_order_release);
>     atomic_store_explicit(y,1,memory_order_relaxed);
>   }
>   
>   P1 (atomic_int* y,atomic_int* x) {
>     atomic_fetch_add_explicit(y,1,memory_order_relaxed);  // STADD
>     atomic_thread_fence(memory_order_acquire);
>     int r0 = atomic_load_explicit(x,memory_order_relaxed);
>   }
>   
>   P2 (atomic_int* y) {
>     int r1 = atomic_load_explicit(y,memory_order_relaxed);
>   }
> 
> 
> My understanding is that it is forbidden for r0 == 0 and r1 == 2 after
>  this test has executed. However, if the relaxed add in P1 <https://reviews.llvm.org/P1> compiles to
>  STADD and the subsequent acquire fence is compiled as DMB LD, then we
>  don't have any ordering guarantees in P1 <https://reviews.llvm.org/P1> and the forbidden result could
>  be observed.


Repository:
  rL LLVM

https://reviews.llvm.org/D58348

Files:
  lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
  test/CodeGen/AArch64/atomic-ops-lse.ll

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