[PATCH] D58343: Enablement for AMD znver2 architecture - skeleton patch

[Ganesh Gopalasubramanian via Phabricator via llvm-commits]

GGanesh created this revision.
GGanesh added reviewers: RKSimon, craig.topper.
GGanesh added a project: LLVM.
Herald added subscribers: llvm-commits, kristina.

This patch enables the following

1. AMD family 17h "znver2" tune flag (-march, -mcpu).
2. ISAs that are enabled for "znver2" architecture.
3. For the time being, it uses the znver1 scheduler model.
4. Tests are updated.


Repository:
  rL LLVM

https://reviews.llvm.org/D58343

Files:
  include/llvm/Support/X86TargetParser.def
  lib/Support/Host.cpp
  lib/Target/X86/X86.td
  test/CodeGen/X86/cpus-amd.ll
  test/CodeGen/X86/lzcnt-zext-cmp.ll
  test/CodeGen/X86/slow-unaligned-mem.ll
  test/CodeGen/X86/x86-64-double-shifts-var.ll

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