[PATCH] D50496: [RISCV] Implment pseudo instructions for load/store from a symbol address.

[James Clarke via Phabricator via llvm-commits]

jrtc27 added inline comments.


================
Comment at: lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:1503
 
+
+void RISCVAsmParser::emitLoadStoreSymbol(MCInst &Inst, unsigned Opcode,
----------------
Extra blank line is not necessary


================
Comment at: lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:1515
+  MCOperand DestReg = Inst.getOperand(0);
+  unsigned SymolOpIdx = HasTmpReg ? 2 : 1;
+  unsigned TmpRegOpIdx = HasTmpReg ? 1 : 0;
----------------
Typo: should be `SymbolOpIdx`


================
Comment at: lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:1558
+  case RISCV::PseudoLB:
+    emitLoadStoreSymbol(Inst, RISCV::LB, IDLoc, Out, /*HasTmpReg*/ false);
+    return false;
----------------
The most common convention in the code base by my limited grepping is `/*HasTmpReg=*/false`; that's certainly most common in the RISC-V backend.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D50496/new/

https://reviews.llvm.org/D50496