[llvm] r354115 - [ARM GlobalISel] Style fix. NFCI

[Diana Picus via llvm-commits]

Author: rovka
Date: Fri Feb 15 02:50:02 2019
New Revision: 354115

URL: http://llvm.org/viewvc/llvm-project?rev=354115&view=rev
Log:
[ARM GlobalISel] Style fix. NFCI

Add the opcode for ADDrr / t2ADDrr to the Opcode cache, as we did for
all other opcodes where the handling is otherwise the same between arm
mode and thumb2.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp?rev=354115&r1=354114&r2=354115&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp Fri Feb 15 02:50:02 2019
@@ -97,6 +97,8 @@ private:
     unsigned STORE8;
     unsigned LOAD8;
 
+    unsigned ADDrr;
+
     // Used for G_ICMP
     unsigned CMPrr;
     unsigned MOVi;
@@ -297,6 +299,8 @@ ARMInstructionSelector::OpcodeCache::Opc
   STORE_OPCODE(STORE8, STRBi12);
   STORE_OPCODE(LOAD8, LDRBi12);
 
+  STORE_OPCODE(ADDrr, ADDrr);
+
   STORE_OPCODE(CMPrr, CMPrr);
   STORE_OPCODE(MOVi, MOVi);
   STORE_OPCODE(MOVCCi, MOVCCi);
@@ -957,7 +961,7 @@ bool ARMInstructionSelector::select(Mach
     return selectShift(ARM_AM::ShiftOpc::lsl, MIB);
   }
   case G_GEP:
-    I.setDesc(TII.get(STI.isThumb2() ? ARM::t2ADDrr : ARM::ADDrr));
+    I.setDesc(TII.get(Opcodes.ADDrr));
     MIB.add(predOps(ARMCC::AL)).add(condCodeOp());
     break;
   case G_FRAME_INDEX: