[PATCH] D58066: [MCA][Scheduler] Use latency information to further classify busy instructions.

[Andrea Di Biagio via Phabricator via llvm-commits]

andreadb marked 2 inline comments as done.
andreadb added inline comments.


================
Comment at: include/llvm/MCA/HardwareUnits/Scheduler.h:98
   std::vector<InstRef> ReadySet;
   std::vector<InstRef> IssuedSet;
 
----------------
RKSimon wrote:
> If possible it'd be useful to comment these sets and explain their relationship to the Instruction::InstrStage enum values
Sure. I will add a comment.


================
Comment at: lib/MCA/Instruction.cpp:161
   // A partial register write cannot complete before a dependent write.
-  auto IsDefReady = [&](const WriteState &Def) {
-    if (!Def.getDependentWrite()) {
-      unsigned CyclesLeft = Def.getDependentWriteCyclesLeft();
-      return !CyclesLeft || CyclesLeft < getLatency();
-    }
+  auto IsDefReady = [&](const WriteState &Def) { return Def.isReady(); };
+
----------------
courbet wrote:
> the capture is no longer needed.
Nice catch. I will fix it. Thanks


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D58066/new/

https://reviews.llvm.org/D58066