[PATCH] D58031: [ARM GlobalISel] Make arm_i32imm an IntImmLeaf

[Diana Picus via Phabricator via llvm-commits]

rovka created this revision.
rovka added a reviewer: eliben.
Herald added subscribers: Petar.Avramovic, hiraditya, kristof.beyls, javed.absar.
Herald added a project: LLVM.

r353501 made it possible to check for the useMovt subtarget
feature without accessing the MachineFunction. Therefore, we
can rewrite the arm_i32imm definition as an IntImmLeaf instead
of a PatLeaf to reduce some of the boilerplate.

Note however that there is currently no support for a GlobalISel-specific
ImmediateCode field, so we must use the same custom code for both
GlobalISel and DAGISel. This gets rid of some duplication in the TableGen
definition, but it forces us to keep both a pointer and a reference to the
subtarget in the ARMInstructionSelector.

That is pretty ugly but it might be a reasonable trade-off, since the TableGen
descriptions should outlive the code in the selector (or in the worst case we
can update to use just the reference when we get rid of DAGISel).


Repository:
  rL LLVM

https://reviews.llvm.org/D58031

Files:
  llvm/lib/Target/ARM/ARMInstrInfo.td
  llvm/lib/Target/ARM/ARMInstructionSelector.cpp


Index: llvm/lib/Target/ARM/ARMInstructionSelector.cpp
===================================================================
--- llvm/lib/Target/ARM/ARMInstructionSelector.cpp
+++ llvm/lib/Target/ARM/ARMInstructionSelector.cpp
@@ -75,6 +75,11 @@
   const ARMRegisterBankInfo &RBI;
   const ARMSubtarget &STI;
 
+  // FIXME: This is necessary because DAGISel uses "Subtarget->" and GlobalISel
+  // uses "STI." in the code generated by TableGen. If we want to reuse some of
+  // the custom C++ predicates written for DAGISel, we need to have both around.
+  const ARMSubtarget *Subtarget = &STI;
+
   // Store the opcodes that we might need, so we don't have to check what kind
   // of subtarget (ARM vs Thumb) we have all the time.
   struct OpcodeCache {
Index: llvm/lib/Target/ARM/ARMInstrInfo.td
===================================================================
--- llvm/lib/Target/ARM/ARMInstrInfo.td
+++ llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -717,23 +717,11 @@
 }
 
 /// arm_i32imm - True for +V6T2, or when isSOImmTwoParVal()
-def arm_i32imm : PatLeaf<(imm), [{
+def arm_i32imm : IntImmLeaf<i32, [{
   if (Subtarget->useMovt())
     return true;
-  return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
-}]> {
-  // Ideally this would be an IntImmLeaf, but then we wouldn't have access to
-  // the MachineFunction.
-  let GISelPredicateCode = [{
-    if (STI.useMovt())
-      return true;
-
-    const auto &MO = MI.getOperand(1);
-    if (!MO.isCImm())
-      return false;
-    return ARM_AM::isSOImmTwoPartVal(MO.getCImm()->getZExtValue());
-  }];
-}
+  return ARM_AM::isSOImmTwoPartVal(Imm.getZExtValue());
+}]>;
 
 /// imm0_1 predicate - Immediate in the range [0,1].
 def Imm0_1AsmOperand: ImmAsmOperand<0,1> { let Name = "Imm0_1"; }


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D58031.186206.patch
Type: text/x-patch
Size: 1759 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20190211/fc440435/attachment.bin>