[PATCH] D58017: [DAG] Add SimplifyDemandedBits support for BSWAP/BITREVERSE

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: efriedma, spatel, arsenm, hfinkel.
Herald added subscribers: jsji, kristof.beyls, tpr, javed.absar, nhaehnle, wdng, jvesely, nemanjai.
Herald added a project: LLVM.

This affects a couple of changes that I need some target-specific advice on:

aarch64 - we're losing this as the zext is being simplified to aext, so the canonicalization fails to confirm that the upper bits are zero. I can try adding a zext(bswap(trunc(x))) variant if that'd be useful as an alternative?

amdgpu - I think these are all benign.

powerpc - this one is annoying, I think simplifying the shifts is enough to cause DAGCombiner::MatchLoadCombine to fail. It might be possible to improve this by adding BSWAP support to calculateByteProvider.


Repository:
  rL LLVM

https://reviews.llvm.org/D58017

Files:
  lib/CodeGen/SelectionDAG/TargetLowering.cpp
  test/CodeGen/AArch64/arm64-rev.ll
  test/CodeGen/AMDGPU/bitreverse.ll
  test/CodeGen/AMDGPU/bswap.ll
  test/CodeGen/PowerPC/pr39478.ll
  test/CodeGen/X86/combine-bitreverse.ll
  test/CodeGen/X86/combine-bswap.ll

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