[llvm] r353648 - [AArch64] Regenerate bswap tests
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sun Feb 10 10:27:37 PST 2019
Author: rksimon
Date: Sun Feb 10 10:27:37 2019
New Revision: 353648
URL: http://llvm.org/viewvc/llvm-project?rev=353648&view=rev
Log:
[AArch64] Regenerate bswap tests
Modified:
llvm/trunk/test/CodeGen/AArch64/arm64-rev.ll
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-rev.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-rev.ll?rev=353648&r1=353647&r2=353648&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-rev.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-rev.ll Sun Feb 10 10:27:37 2019
@@ -1,17 +1,22 @@
-; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64-eabi -aarch64-neon-syntax=apple | FileCheck %s
define i32 @test_rev_w(i32 %a) nounwind {
-entry:
; CHECK-LABEL: test_rev_w:
-; CHECK: rev w0, w0
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: rev w0, w0
+; CHECK-NEXT: ret
+entry:
%0 = tail call i32 @llvm.bswap.i32(i32 %a)
ret i32 %0
}
define i64 @test_rev_x(i64 %a) nounwind {
-entry:
; CHECK-LABEL: test_rev_x:
-; CHECK: rev x0, x0
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: rev x0, x0
+; CHECK-NEXT: ret
+entry:
%0 = tail call i64 @llvm.bswap.i64(i64 %a)
ret i64 %0
}
@@ -19,11 +24,12 @@ entry:
; Canonicalize (srl (bswap x), 16) to (rotr (bswap x), 16) if the high 16-bits
; of %a are zero. This optimizes rev + lsr 16 to rev16.
define i32 @test_rev_w_srl16(i16 %a) {
-entry:
; CHECK-LABEL: test_rev_w_srl16:
-; CHECK: and [[REG:w[0-9]+]], w0, #0xffff
-; CHECK: rev16 w0, [[REG]]
-; CHECK-NOT: lsr
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: and w8, w0, #0xffff
+; CHECK-NEXT: rev16 w0, w8
+; CHECK-NEXT: ret
+entry:
%0 = zext i16 %a to i32
%1 = tail call i32 @llvm.bswap.i32(i32 %0)
%2 = lshr i32 %1, 16
@@ -33,10 +39,12 @@ entry:
; Canonicalize (srl (bswap x), 32) to (rotr (bswap x), 32) if the high 32-bits
; of %a are zero. This optimizes rev + lsr 32 to rev32.
define i64 @test_rev_x_srl32(i32 %a) {
-entry:
; CHECK-LABEL: test_rev_x_srl32:
-; CHECK: rev32 x0, {{x[0-9]+}}
-; CHECK-NOT: lsr
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov w8, w0
+; CHECK-NEXT: rev32 x0, x8
+; CHECK-NEXT: ret
+entry:
%0 = zext i32 %a to i64
%1 = tail call i64 @llvm.bswap.i64(i64 %0)
%2 = lshr i64 %1, 32
@@ -47,9 +55,11 @@ declare i32 @llvm.bswap.i32(i32) nounwin
declare i64 @llvm.bswap.i64(i64) nounwind readnone
define i32 @test_rev16_w(i32 %X) nounwind {
-entry:
; CHECK-LABEL: test_rev16_w:
-; CHECK: rev16 w0, w0
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: rev16 w0, w0
+; CHECK-NEXT: ret
+entry:
%tmp1 = lshr i32 %X, 8
%X15 = bitcast i32 %X to i32
%tmp4 = shl i32 %X15, 8
@@ -67,9 +77,12 @@ entry:
; 01234567 ->(bswap) 76543210 ->(rotr) 10765432
; 01234567 ->(rev16) 10325476
define i64 @test_rev16_x(i64 %a) nounwind {
-entry:
; CHECK-LABEL: test_rev16_x:
-; CHECK-NOT: rev16 x0, x0
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: rev x8, x0
+; CHECK-NEXT: ror x0, x8, #16
+; CHECK-NEXT: ret
+entry:
%0 = tail call i64 @llvm.bswap.i64(i64 %a)
%1 = lshr i64 %0, 16
%2 = shl i64 %0, 48
@@ -78,9 +91,11 @@ entry:
}
define i64 @test_rev32_x(i64 %a) nounwind {
-entry:
; CHECK-LABEL: test_rev32_x:
-; CHECK: rev32 x0, x0
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: rev32 x0, x0
+; CHECK-NEXT: ret
+entry:
%0 = tail call i64 @llvm.bswap.i64(i64 %a)
%1 = lshr i64 %0, 32
%2 = shl i64 %0, 32
@@ -89,112 +104,154 @@ entry:
}
define <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind {
-;CHECK-LABEL: test_vrev64D8:
-;CHECK: rev64.8b
+; CHECK-LABEL: test_vrev64D8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: rev64.8b v0, v0
+; CHECK-NEXT: ret
%tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <8 x i8> %tmp2
}
define <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind {
-;CHECK-LABEL: test_vrev64D16:
-;CHECK: rev64.4h
+; CHECK-LABEL: test_vrev64D16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: rev64.4h v0, v0
+; CHECK-NEXT: ret
%tmp1 = load <4 x i16>, <4 x i16>* %A
%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
ret <4 x i16> %tmp2
}
define <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind {
-;CHECK-LABEL: test_vrev64D32:
-;CHECK: rev64.2s
+; CHECK-LABEL: test_vrev64D32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: rev64.2s v0, v0
+; CHECK-NEXT: ret
%tmp1 = load <2 x i32>, <2 x i32>* %A
%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> <i32 1, i32 0>
ret <2 x i32> %tmp2
}
define <2 x float> @test_vrev64Df(<2 x float>* %A) nounwind {
-;CHECK-LABEL: test_vrev64Df:
-;CHECK: rev64.2s
+; CHECK-LABEL: test_vrev64Df:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: rev64.2s v0, v0
+; CHECK-NEXT: ret
%tmp1 = load <2 x float>, <2 x float>* %A
%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> <i32 1, i32 0>
ret <2 x float> %tmp2
}
define <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind {
-;CHECK-LABEL: test_vrev64Q8:
-;CHECK: rev64.16b
+; CHECK-LABEL: test_vrev64Q8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr q0, [x0]
+; CHECK-NEXT: rev64.16b v0, v0
+; CHECK-NEXT: ret
%tmp1 = load <16 x i8>, <16 x i8>* %A
%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
ret <16 x i8> %tmp2
}
define <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind {
-;CHECK-LABEL: test_vrev64Q16:
-;CHECK: rev64.8h
+; CHECK-LABEL: test_vrev64Q16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr q0, [x0]
+; CHECK-NEXT: rev64.8h v0, v0
+; CHECK-NEXT: ret
%tmp1 = load <8 x i16>, <8 x i16>* %A
%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
ret <8 x i16> %tmp2
}
define <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind {
-;CHECK-LABEL: test_vrev64Q32:
-;CHECK: rev64.4s
+; CHECK-LABEL: test_vrev64Q32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr q0, [x0]
+; CHECK-NEXT: rev64.4s v0, v0
+; CHECK-NEXT: ret
%tmp1 = load <4 x i32>, <4 x i32>* %A
%tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
ret <4 x i32> %tmp2
}
define <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind {
-;CHECK-LABEL: test_vrev64Qf:
-;CHECK: rev64.4s
+; CHECK-LABEL: test_vrev64Qf:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr q0, [x0]
+; CHECK-NEXT: rev64.4s v0, v0
+; CHECK-NEXT: ret
%tmp1 = load <4 x float>, <4 x float>* %A
%tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
ret <4 x float> %tmp2
}
define <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind {
-;CHECK-LABEL: test_vrev32D8:
-;CHECK: rev32.8b
+; CHECK-LABEL: test_vrev32D8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: rev32.8b v0, v0
+; CHECK-NEXT: ret
%tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
ret <8 x i8> %tmp2
}
define <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind {
-;CHECK-LABEL: test_vrev32D16:
-;CHECK: rev32.4h
+; CHECK-LABEL: test_vrev32D16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: rev32.4h v0, v0
+; CHECK-NEXT: ret
%tmp1 = load <4 x i16>, <4 x i16>* %A
%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
ret <4 x i16> %tmp2
}
define <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind {
-;CHECK-LABEL: test_vrev32Q8:
-;CHECK: rev32.16b
+; CHECK-LABEL: test_vrev32Q8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr q0, [x0]
+; CHECK-NEXT: rev32.16b v0, v0
+; CHECK-NEXT: ret
%tmp1 = load <16 x i8>, <16 x i8>* %A
%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
ret <16 x i8> %tmp2
}
define <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind {
-;CHECK-LABEL: test_vrev32Q16:
-;CHECK: rev32.8h
+; CHECK-LABEL: test_vrev32Q16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr q0, [x0]
+; CHECK-NEXT: rev32.8h v0, v0
+; CHECK-NEXT: ret
%tmp1 = load <8 x i16>, <8 x i16>* %A
%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
ret <8 x i16> %tmp2
}
define <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind {
-;CHECK-LABEL: test_vrev16D8:
-;CHECK: rev16.8b
+; CHECK-LABEL: test_vrev16D8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: rev16.8b v0, v0
+; CHECK-NEXT: ret
%tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
ret <8 x i8> %tmp2
}
define <16 x i8> @test_vrev16Q8(<16 x i8>* %A) nounwind {
-;CHECK-LABEL: test_vrev16Q8:
-;CHECK: rev16.16b
+; CHECK-LABEL: test_vrev16Q8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr q0, [x0]
+; CHECK-NEXT: rev16.16b v0, v0
+; CHECK-NEXT: ret
%tmp1 = load <16 x i8>, <16 x i8>* %A
%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
ret <16 x i8> %tmp2
@@ -203,16 +260,22 @@ define <16 x i8> @test_vrev16Q8(<16 x i8
; Undef shuffle indices should not prevent matching to VREV:
define <8 x i8> @test_vrev64D8_undef(<8 x i8>* %A) nounwind {
-;CHECK-LABEL: test_vrev64D8_undef:
-;CHECK: rev64.8b
+; CHECK-LABEL: test_vrev64D8_undef:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: rev64.8b v0, v0
+; CHECK-NEXT: ret
%tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 undef, i32 undef, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <8 x i8> %tmp2
}
define <8 x i16> @test_vrev32Q16_undef(<8 x i16>* %A) nounwind {
-;CHECK-LABEL: test_vrev32Q16_undef:
-;CHECK: rev32.8h
+; CHECK-LABEL: test_vrev32Q16_undef:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr q0, [x0]
+; CHECK-NEXT: rev32.8h v0, v0
+; CHECK-NEXT: ret
%tmp1 = load <8 x i16>, <8 x i16>* %A
%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 undef, i32 0, i32 undef, i32 2, i32 5, i32 4, i32 7, i32 undef>
ret <8 x i16> %tmp2
@@ -221,9 +284,12 @@ define <8 x i16> @test_vrev32Q16_undef(<
; vrev <4 x i16> should use REV32 and not REV64
define void @test_vrev64(<4 x i16>* nocapture %source, <2 x i16>* nocapture %dst) nounwind ssp {
; CHECK-LABEL: test_vrev64:
-; CHECK: ldr [[DEST:q[0-9]+]],
-; CHECK: st1.h
-; CHECK: st1.h
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr q0, [x0]
+; CHECK-NEXT: add x8, x1, #2 // =2
+; CHECK-NEXT: st1.h { v0 }[5], [x8]
+; CHECK-NEXT: st1.h { v0 }[6], [x1]
+; CHECK-NEXT: ret
entry:
%0 = bitcast <4 x i16>* %source to <8 x i16>*
%tmp2 = load <8 x i16>, <8 x i16>* %0, align 4
@@ -237,9 +303,15 @@ entry:
; Test vrev of float4
define void @float_vrev64(float* nocapture %source, <4 x float>* nocapture %dest) nounwind noinline ssp {
-; CHECK: float_vrev64
-; CHECK: ldr [[DEST:q[0-9]+]],
-; CHECK: rev64.4s
+; CHECK-LABEL: float_vrev64:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr q0, [x0]
+; CHECK-NEXT: movi.2d v1, #0000000000000000
+; CHECK-NEXT: dup.4s v1, v1[0]
+; CHECK-NEXT: ext.16b v0, v0, v1, #12
+; CHECK-NEXT: rev64.4s v0, v0
+; CHECK-NEXT: str q0, [x1, #176]
+; CHECK-NEXT: ret
entry:
%0 = bitcast float* %source to <4 x float>*
%tmp2 = load <4 x float>, <4 x float>* %0, align 4
@@ -252,9 +324,9 @@ entry:
define <4 x i32> @test_vrev32_bswap(<4 x i32> %source) nounwind {
; CHECK-LABEL: test_vrev32_bswap:
-; CHECK: rev32.16b
-; CHECK-NOT: rev
-; CHECK: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: rev32.16b v0, v0
+; CHECK-NEXT: ret
%bswap = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %source)
ret <4 x i32> %bswap
}
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