[PATCH] D57644: [X86] Add ST0 as an implicit def/use of x87 load/store instructions during FP stackifying.

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This revision was automatically updated to reflect the committed changes.
Closed by commit rL353070: [X86] Add ST0 as an implicit def/use of x87 load/store instructions during FP… (authored by ctopper, committed by ).

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D57644/new/

https://reviews.llvm.org/D57644

Files:
  llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp
  llvm/trunk/test/CodeGen/X86/pr40539.ll


Index: llvm/trunk/test/CodeGen/X86/pr40539.ll
===================================================================
--- llvm/trunk/test/CodeGen/X86/pr40539.ll
+++ llvm/trunk/test/CodeGen/X86/pr40539.ll
@@ -1,9 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mcpu=pentium4 | FileCheck %s
 
-; FIXME: The fstps in the following test case should be between the inline
-; assembly expansion and the cmpeqss. The postRA scheduler has rearranged them.
-
 @f1 = global float 1.000000e+00, align 4
 
 define zeroext i1 @_Z9test_log2v() {
@@ -12,13 +9,13 @@
 ; CHECK-NEXT:    pushl %eax
 ; CHECK-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-NEXT:    flds f1
-; CHECK-NEXT:    fstps (%esp)
-; CHECK-NEXT:    xorps %xmm0, %xmm0
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    fld1
 ; CHECK-NEXT:    fxch %st(1)
 ; CHECK-NEXT:    fyl2x
 ; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    fstps (%esp)
+; CHECK-NEXT:    xorps %xmm0, %xmm0
 ; CHECK-NEXT:    cmpeqss (%esp), %xmm0
 ; CHECK-NEXT:    movd %xmm0, %eax
 ; CHECK-NEXT:    andl $1, %eax
@@ -44,12 +41,12 @@
 ; CHECK-NEXT:    .cfi_def_cfa_offset 12
 ; CHECK-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; CHECK-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; CHECK-NEXT:    #APP
-; CHECK-NEXT:    fcos
-; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    divss {{\.LCPI.*}}, %xmm0
 ; CHECK-NEXT:    movss %xmm0, {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    flds {{[0-9]+}}(%esp)
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    fcos
+; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    fstps (%esp)
 ; CHECK-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; CHECK-NEXT:    ucomiss %xmm0, %xmm1
Index: llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp
===================================================================
--- llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp
+++ llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp
@@ -1095,6 +1095,8 @@
   // Change from the pseudo instruction to the concrete instruction.
   MI.RemoveOperand(0); // Remove the explicit ST(0) operand
   MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode())));
+  MI.addOperand(
+      MachineOperand::CreateReg(X86::ST0, /*isDef*/ true, /*isImp*/ true));
 
   // Result gets pushed on the stack.
   pushReg(DestReg);
@@ -1139,6 +1141,8 @@
   // Convert from the pseudo instruction to the concrete instruction.
   MI.RemoveOperand(NumOps - 1); // Remove explicit ST(0) operand
   MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode())));
+  MI.addOperand(
+      MachineOperand::CreateReg(X86::ST0, /*isDef*/ false, /*isImp*/ true));
 
   if (MI.getOpcode() == X86::IST_FP64m || MI.getOpcode() == X86::ISTT_FP16m ||
       MI.getOpcode() == X86::ISTT_FP32m || MI.getOpcode() == X86::ISTT_FP64m ||


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