[PATCH] D53235: [RISCV] Add RV64F codegen support

[Alex Bradbury via Phabricator via llvm-commits]

asb marked an inline comment as done.
asb added inline comments.


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Comment at: lib/Target/RISCV/RISCVInstrInfoF.td:372
+def : Pat<(sext_inreg (zexti32 (fp_to_uint FPR32:$rs1)), i32),
+          (FCVT_WU_S $rs1, 0b001)>;
+
----------------
efriedma wrote:
> This is supposed to be assertzexti32, as opposed to zexti32, right?  I doubt it has any practical impact because an "AND" would be dead, but better to be clear.
Yes, the AND would be dead but as you suggest it's better to stick with assertzexti32 so people don't need to evaluate whether the AND pattern is dead and unnecessary when reading the code.

I'll adjust when committing - thanks.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D53235/new/

https://reviews.llvm.org/D53235