[PATCH] D53235: [RISCV] Add RV64F codegen support

[Alex Bradbury via Phabricator via llvm-commits]

asb updated this revision to Diff 184533.
asb marked an inline comment as done.
asb added a comment.

Hi Eli. Thanks, as always, for the careful review. I've opted to introduce a SEXT_IN_REG in this case, and instead define a target-specific node that produces an anyext result (and a pattern that ensures FMV_X_W is selected for (sexti32 (riscv_fmv_x_anyextw_rv64 ..)). Otherwise there are cases where we end up with an unwanted sext.w in cases where redundant GPR->FPR->GPR moves have been eliminated.

For this reason I think this is the more useful semantic, and I believe it's safe based on my understanding of the legalisation+widening expectations but I'd really welcome a second opinion.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D53235/new/

https://reviews.llvm.org/D53235

Files:
  lib/Target/RISCV/RISCVISelLowering.cpp
  lib/Target/RISCV/RISCVISelLowering.h
  lib/Target/RISCV/RISCVInstrInfoF.td
  test/CodeGen/RISCV/float-arith.ll
  test/CodeGen/RISCV/float-bitmanip-dagcombines.ll
  test/CodeGen/RISCV/float-br-fcmp.ll
  test/CodeGen/RISCV/float-convert.ll
  test/CodeGen/RISCV/float-fcmp.ll
  test/CodeGen/RISCV/float-imm.ll
  test/CodeGen/RISCV/float-mem.ll
  test/CodeGen/RISCV/float-select-fcmp.ll
  test/CodeGen/RISCV/rv32i-rv64i-float-double.ll
  test/CodeGen/RISCV/rv64f-float-convert.ll

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