[llvm] r352583 - [PowerPC] more opportunity for converting reg+reg to reg+imm

[Chen Zheng via llvm-commits]

Author: shchenz
Date: Tue Jan 29 17:57:01 2019
New Revision: 352583

URL: http://llvm.org/viewvc/llvm-project?rev=352583&view=rev
Log:
[PowerPC] more opportunity for converting reg+reg to reg+imm
Differential Revision: https://reviews.llvm.org/D57314

Added:
    llvm/trunk/test/CodeGen/PowerPC/convert-rr-to-ri-instr-add.mir
Modified:
    llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp

Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=352583&r1=352582&r2=352583&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Tue Jan 29 17:57:01 2019
@@ -3205,9 +3205,9 @@ bool PPCInstrInfo::isRegElgibleForForwar
   }
   assert((&*It) == &DefMI && "DefMI is missing");
 
-  // If DefMI also uses the register to be forwarded, we can only forward it
+  // If DefMI also defines the register to be forwarded, we can only forward it
   // if DefMI is being erased.
-  if (DefMI.readsRegister(Reg, &getRegisterInfo()))
+  if (DefMI.modifiesRegister(Reg, &getRegisterInfo()))
     return KillDefMI;
 
   return true;

Added: llvm/trunk/test/CodeGen/PowerPC/convert-rr-to-ri-instr-add.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/convert-rr-to-ri-instr-add.mir?rev=352583&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/convert-rr-to-ri-instr-add.mir (added)
+++ llvm/trunk/test/CodeGen/PowerPC/convert-rr-to-ri-instr-add.mir Tue Jan 29 17:57:01 2019
@@ -0,0 +1,17 @@
+# RUN: llc -mtriple=powerpc64le--linux-gnu -stop-after ppc-pre-emit-peephole %s -o - -verify-machineinstrs | FileCheck %s
+
+---
+# ADDI8 + STFSX can be converted to ADDI8 + STFS even ADDI8 can not be erased.
+name: testFwdOperandKilledAfter
+# CHECK: name: testFwdOperandKilledAfter
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+    liveins: $x3, $f1, $x5
+    $x3 = ADDI8 $x5, 100
+    STFSX killed $f1, $zero8, $x3
+    ; CHECK: STFS killed $f1, 100, $x5
+    STD killed $x3, killed $x5, 100
+    ; CHECK: STD killed $x3, killed $x5, 100
+    BLR8 implicit $lr8, implicit $rm
+...