[PATCH] D57300: [X86][BdVer2] Transfer delays from the integer to the floating point unit.

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri created this revision.
lebedev.ri added reviewers: andreadb, RKSimon, craig.topper.
Herald added subscribers: courbet, gbedwell.
lebedev.ri edited the summary of this revision.

I'm unable to find this number in the "AMD SOG for family 15h".
llvm-exegesis measures the latencies of these instructions as `2`,
which matches the latencies specified in "AMD SOG for family 15h".

However if we look at Agner, Microarchitecture, "AMD Bulldozer, Piledriver,
Steamroller and Excavator pipeline", "Data delay between different execution
domains", the int->ivec transfer is listed as `8`..`10`cy of additional latency.

Also, Agner's "Instruction tables", for Piledriver, lists their latencies as `12`,
which is consistent with `2cy` from exegesis / AMD SOG + `10cy` transfer delay.

Additional data point comes from the fact that Agner's "Instruction tables",
for Jaguar, lists their latencies as `8`; and "AMD SOG for family 16h" does
state the `+6cy` int->ivec delay, which is consistent with instr latency of `1` or `2`.


Repository:
  rL LLVM

https://reviews.llvm.org/D57300

Files:
  lib/Target/X86/X86ScheduleBdVer2.td
  test/CodeGen/X86/mmx-schedule.ll
  test/CodeGen/X86/sse2-schedule.ll
  test/CodeGen/X86/sse41-schedule.ll
  test/tools/llvm-mca/X86/BdVer2/int-to-fpu-forwarding-1.s
  test/tools/llvm-mca/X86/BdVer2/int-to-fpu-forwarding-3.s
  test/tools/llvm-mca/X86/BdVer2/resources-avx1.s
  test/tools/llvm-mca/X86/BdVer2/resources-sse1.s
  test/tools/llvm-mca/X86/BdVer2/resources-sse2.s
  test/tools/llvm-mca/X86/BdVer2/resources-sse41.s

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