[llvm] r352312 - Re-apply "r351584: "GlobalISel: Verify g_zextload and g_sextload""

[Amara Emerson via llvm-commits]

Author: aemerson
Date: Sun Jan 27 03:34:41 2019
New Revision: 352312

URL: http://llvm.org/viewvc/llvm-project?rev=352312&view=rev
Log:
Re-apply "r351584: "GlobalISel: Verify g_zextload and g_sextload""

I reverted it originally due to a bot failing. The underlying bug has been fixed
as of r352311.

Added:
    llvm/trunk/test/CodeGen/MIR/AArch64/invalid-extload.mir
Modified:
    llvm/trunk/lib/CodeGen/MachineVerifier.cpp

Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=352312&r1=352311&r2=352312&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Sun Jan 27 03:34:41 2019
@@ -1002,11 +1002,24 @@ void MachineVerifier::visitMachineInstrB
   }
   case TargetOpcode::G_LOAD:
   case TargetOpcode::G_STORE:
+  case TargetOpcode::G_ZEXTLOAD:
+  case TargetOpcode::G_SEXTLOAD:
     // Generic loads and stores must have a single MachineMemOperand
     // describing that access.
-    if (!MI->hasOneMemOperand())
+    if (!MI->hasOneMemOperand()) {
       report("Generic instruction accessing memory must have one mem operand",
              MI);
+    } else {
+      if (MI->getOpcode() == TargetOpcode::G_ZEXTLOAD ||
+          MI->getOpcode() == TargetOpcode::G_SEXTLOAD) {
+        const MachineMemOperand &MMO = **MI->memoperands_begin();
+        LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
+        if (MMO.getSize() * 8 >= DstTy.getSizeInBits()) {
+          report("Generic extload must have a narrower memory type", MI);
+        }
+      }
+    }
+
     break;
   case TargetOpcode::G_PHI: {
     LLT DstTy = MRI->getType(MI->getOperand(0).getReg());

Added: llvm/trunk/test/CodeGen/MIR/AArch64/invalid-extload.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AArch64/invalid-extload.mir?rev=352312&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AArch64/invalid-extload.mir (added)
+++ llvm/trunk/test/CodeGen/MIR/AArch64/invalid-extload.mir Sun Jan 27 03:34:41 2019
@@ -0,0 +1,23 @@
+# RUN: not llc -mtriple=aarch64-none-linux-gnu -run-pass none -o - %s 2>&1 | FileCheck %s
+
+# CHECK: *** Bad machine code: Generic extload must have a narrower memory type ***
+# CHECK: *** Bad machine code: Generic extload must have a narrower memory type ***
+# CHECK: *** Bad machine code: Generic extload must have a narrower memory type ***
+# CHECK: *** Bad machine code: Generic extload must have a narrower memory type ***
+# CHECK: *** Bad machine code: Generic instruction accessing memory must have one mem operand ***
+# CHECK: *** Bad machine code: Generic instruction accessing memory must have one mem operand ***
+
+---
+name: invalid_extload_memory_sizes
+body: |
+  bb.0:
+
+    %0:_(p0) = COPY $x0
+    %1:_(s64) = G_ZEXTLOAD %0(p0) :: (load 8)
+    %2:_(s64) = G_ZEXTLOAD %0(p0) :: (load 16)
+    %3:_(s64) = G_SEXTLOAD %0(p0) :: (load 8)
+    %4:_(s64) = G_SEXTLOAD %0(p0) :: (load 16)
+    %5:_(s64) = G_ZEXTLOAD %0(p0)
+    %6:_(s64) = G_SEXTLOAD %0(p0)
+
+...