[PATCH] D53235: [RISCV] Add RV64F codegen support

[Alex Bradbury via Phabricator via llvm-commits]

asb added inline comments.


================
Comment at: test/CodeGen/RISCV/float-arith.ll:148
+; RV64IF-NEXT:    fmv.x.w a0, ft0
+; RV64IF-NEXT:    ret
   %1 = fsub float -0.0, %a
----------------
jrtc27 wrote:
> lewis-revill wrote:
> > Can RV64 employ the same technique as RV32 here, and for other similar DAG combines? I'm guessing cost-wise it would be desirable to do so.
> It should work, since `fmv.x.w` sign-extends:
> 
> > For RV64, the higher 32 bits of the destination register are filled with copies of the floating-point number’s sign bit.
> 
> and the `lui` will also sign-extend, so `xor` will flip all the higher bits too.
I've split out float-bitmanip-dagcombines.ll and double-bitmanip-dagcombines.ll to better demonstrate the opportunities here. One RV32F, target-independent code provides the combine for us. As we need to use RISCVISD::FMV_X_W_RV64 (as bitcasting to i32 wouldn't be legal), we need to provide an equivalent combine in the RISC-V backend. I've updated the patch to do so.


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  https://reviews.llvm.org/D53235/new/

https://reviews.llvm.org/D53235