[llvm] r351485 - [mips] Emit .reloc R_{MICRO}MIPS_JALR along with j(al)r(c) $25
Hans Wennborg via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 24 16:12:04 PST 2019
Merged to 8.0 in r352137.
On Thu, Jan 17, 2019 at 1:54 PM Vladimir Stefanovic via llvm-commits
<llvm-commits at lists.llvm.org> wrote:
>
> Author: vstefanovic
> Date: Thu Jan 17 13:50:37 2019
> New Revision: 351485
>
> URL: http://llvm.org/viewvc/llvm-project?rev=351485&view=rev
> Log:
> [mips] Emit .reloc R_{MICRO}MIPS_JALR along with j(al)r(c) $25
>
> The callee address is added as an optional operand (MCSymbol) in
> AdjustInstrPostInstrSelection() and then used by asm printer to insert:
> '.reloc tmplabel, R_MIPS_JALR, symbol
> tmplabel:'.
> Controlled with '-mips-jalr-reloc', default is true.
>
> Differential revision: https://reviews.llvm.org/D56694
>
> Added:
> llvm/trunk/test/CodeGen/Mips/reloc-jalr.ll
> Modified:
> llvm/trunk/lib/CodeGen/MachineInstr.cpp
> llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
> llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
> llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h
> llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td
> llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
> llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td
> llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp
> llvm/trunk/lib/Target/Mips/MipsFastISel.cpp
> llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
> llvm/trunk/lib/Target/Mips/MipsISelLowering.h
> llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
> llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
> llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp
> llvm/trunk/test/CodeGen/Mips/cconv/vector.ll
> llvm/trunk/test/CodeGen/Mips/gprestore.ll
> llvm/trunk/test/CodeGen/Mips/llvm-ir/sdiv.ll
> llvm/trunk/test/CodeGen/Mips/llvm-ir/srem.ll
> llvm/trunk/test/CodeGen/Mips/llvm-ir/udiv.ll
> llvm/trunk/test/CodeGen/Mips/llvm-ir/urem.ll
> llvm/trunk/test/CodeGen/Mips/long-call-attr.ll
> llvm/trunk/test/CodeGen/Mips/long-call-mcount.ll
> llvm/trunk/test/CodeGen/Mips/msa/f16-llvm-ir.ll
> llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll
> llvm/trunk/test/CodeGen/Mips/shrink-wrapping.ll
>
> Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=351485&r1=351484&r2=351485&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original)
> +++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Thu Jan 17 13:50:37 2019
> @@ -225,12 +225,13 @@ void MachineInstr::addOperand(MachineFun
> }
>
> #ifndef NDEBUG
> - bool isMetaDataOp = Op.getType() == MachineOperand::MO_Metadata;
> + bool isDebugOp = Op.getType() == MachineOperand::MO_Metadata ||
> + Op.getType() == MachineOperand::MO_MCSymbol;
> // OpNo now points as the desired insertion point. Unless this is a variadic
> // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
> // RegMask operands go between the explicit and implicit operands.
> assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||
> - OpNo < MCID->getNumOperands() || isMetaDataOp) &&
> + OpNo < MCID->getNumOperands() || isDebugOp) &&
> "Trying to add an operand to a machine instr that is already done!");
> #endif
>
>
> Modified: llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp?rev=351485&r1=351484&r2=351485&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Thu Jan 17 13:50:37 2019
> @@ -65,10 +65,7 @@ class MCInstrInfo;
>
> } // end namespace llvm
>
> -static cl::opt<bool>
> -EmitJalrReloc("mips-jalr-reloc", cl::Hidden,
> - cl::desc("MIPS: Emit R_{MICRO}MIPS_JALR relocation with jalr"),
> - cl::init(true));
> +extern cl::opt<bool> EmitJalrReloc;
>
> namespace {
>
>
> Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp?rev=351485&r1=351484&r2=351485&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp Thu Jan 17 13:50:37 2019
> @@ -15,6 +15,13 @@
>
> using namespace llvm;
>
> +// Note: this option is defined here to be visible from libLLVMMipsAsmParser
> +// and libLLVMMipsCodeGen
> +cl::opt<bool>
> +EmitJalrReloc("mips-jalr-reloc", cl::Hidden,
> + cl::desc("MIPS: Emit R_{MICRO}MIPS_JALR relocation with jalr"),
> + cl::init(true));
> +
> namespace {
> static const MCPhysReg O32IntRegs[4] = {Mips::A0, Mips::A1, Mips::A2, Mips::A3};
>
>
> Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h?rev=351485&r1=351484&r2=351485&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h (original)
> +++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h Thu Jan 17 13:50:37 2019
> @@ -89,7 +89,10 @@ namespace MipsII {
> MO_GOT_HI16,
> MO_GOT_LO16,
> MO_CALL_HI16,
> - MO_CALL_LO16
> + MO_CALL_LO16,
> +
> + /// Helper operand used to generate R_MIPS_JALR
> + MO_JALR
> };
>
> enum {
>
> Modified: llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td?rev=351485&r1=351484&r2=351485&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td (original)
> +++ llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td Thu Jan 17 13:50:37 2019
> @@ -460,6 +460,7 @@ class JALRC16_MMR6_DESC_BASE<string opst
> let isCall = 1;
> let hasDelaySlot = 0;
> let Defs = [RA];
> + let hasPostISelHook = 1;
> }
> class JALRC16_MMR6_DESC : JALRC16_MMR6_DESC_BASE<"jalr", GPR32Opnd>;
>
>
> Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td?rev=351485&r1=351484&r2=351485&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td Thu Jan 17 13:50:37 2019
> @@ -426,6 +426,7 @@ class JumpLinkRegMM16<string opstr, Regi
> let isCall = 1;
> let hasDelaySlot = 1;
> let Defs = [RA];
> + let hasPostISelHook = 1;
> }
>
> // 16-bit Jump Reg
>
> Modified: llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td?rev=351485&r1=351484&r2=351485&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td (original)
> +++ llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td Thu Jan 17 13:50:37 2019
> @@ -1105,7 +1105,7 @@ def : MipsPat<(select i32:$cond, immz, i
>
> // Pseudo instructions
> let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
> - hasExtraSrcRegAllocReq = 1, isCTI = 1, Defs = [AT] in {
> + hasExtraSrcRegAllocReq = 1, isCTI = 1, Defs = [AT], hasPostISelHook = 1 in {
> class TailCallRegR6<Instruction JumpInst, Register RT, RegisterOperand RO> :
> PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], II_JR>,
> PseudoInstExpansion<(JumpInst RT:$rt, RO:$rs)>;
>
> Modified: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp?rev=351485&r1=351484&r2=351485&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp Thu Jan 17 13:50:37 2019
> @@ -68,6 +68,8 @@ using namespace llvm;
>
> #define DEBUG_TYPE "mips-asm-printer"
>
> +extern cl::opt<bool> EmitJalrReloc;
> +
> MipsTargetStreamer &MipsAsmPrinter::getTargetStreamer() const {
> return static_cast<MipsTargetStreamer &>(*OutStreamer->getTargetStreamer());
> }
> @@ -148,6 +150,40 @@ void MipsAsmPrinter::emitPseudoIndirectB
> EmitToStreamer(OutStreamer, TmpInst0);
> }
>
> +// If there is an MO_JALR operand, insert:
> +//
> +// .reloc tmplabel, R_{MICRO}MIPS_JALR, symbol
> +// tmplabel:
> +//
> +// This is an optimization hint for the linker which may then replace
> +// an indirect call with a direct branch.
> +static void emitDirectiveRelocJalr(const MachineInstr &MI,
> + MCContext &OutContext,
> + TargetMachine &TM,
> + MCStreamer &OutStreamer,
> + const MipsSubtarget &Subtarget) {
> + for (unsigned int I = MI.getDesc().getNumOperands(), E = MI.getNumOperands();
> + I < E; ++I) {
> + MachineOperand MO = MI.getOperand(I);
> + if (MO.isMCSymbol() && (MO.getTargetFlags() & MipsII::MO_JALR)) {
> + MCSymbol *Callee = MO.getMCSymbol();
> + if (Callee && !Callee->getName().empty()) {
> + MCSymbol *OffsetLabel = OutContext.createTempSymbol();
> + const MCExpr *OffsetExpr =
> + MCSymbolRefExpr::create(OffsetLabel, OutContext);
> + const MCExpr *CaleeExpr =
> + MCSymbolRefExpr::create(Callee, OutContext);
> + OutStreamer.EmitRelocDirective
> + (*OffsetExpr,
> + Subtarget.inMicroMipsMode() ? "R_MICROMIPS_JALR" : "R_MIPS_JALR",
> + CaleeExpr, SMLoc(), *TM.getMCSubtargetInfo());
> + OutStreamer.EmitLabel(OffsetLabel);
> + return;
> + }
> + }
> + }
> +}
> +
> void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
> MipsTargetStreamer &TS = getTargetStreamer();
> unsigned Opc = MI->getOpcode();
> @@ -207,6 +243,11 @@ void MipsAsmPrinter::EmitInstruction(con
> return;
> }
>
> + if (EmitJalrReloc &&
> + (MI->isReturn() || MI->isCall() || MI->isIndirectBranch())) {
> + emitDirectiveRelocJalr(*MI, OutContext, TM, *OutStreamer, *Subtarget);
> + }
> +
> MachineBasicBlock::const_instr_iterator I = MI->getIterator();
> MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
>
>
> Modified: llvm/trunk/lib/Target/Mips/MipsFastISel.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsFastISel.cpp?rev=351485&r1=351484&r2=351485&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsFastISel.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/MipsFastISel.cpp Thu Jan 17 13:50:37 2019
> @@ -56,6 +56,7 @@
> #include "llvm/IR/Type.h"
> #include "llvm/IR/User.h"
> #include "llvm/IR/Value.h"
> +#include "llvm/MC/MCContext.h"
> #include "llvm/MC/MCInstrDesc.h"
> #include "llvm/MC/MCRegisterInfo.h"
> #include "llvm/MC/MCSymbol.h"
> @@ -75,6 +76,8 @@
>
> using namespace llvm;
>
> +extern cl::opt<bool> EmitJalrReloc;
> +
> namespace {
>
> class MipsFastISel final : public FastISel {
> @@ -1551,6 +1554,16 @@ bool MipsFastISel::fastLowerCall(CallLow
>
> CLI.Call = MIB;
>
> + if (EmitJalrReloc && !Subtarget->inMips16Mode()) {
> + // Attach callee address to the instruction, let asm printer emit
> + // .reloc R_MIPS_JALR.
> + if (Symbol)
> + MIB.addSym(Symbol, MipsII::MO_JALR);
> + else
> + MIB.addSym(FuncInfo.MF->getContext().getOrCreateSymbol(
> + Addr.getGlobalValue()->getName()), MipsII::MO_JALR);
> + }
> +
> // Finish off the call including any return values.
> return finishCall(CLI, RetVT, NumBytes);
> }
>
> Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=351485&r1=351484&r2=351485&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Thu Jan 17 13:50:37 2019
> @@ -57,6 +57,7 @@
> #include "llvm/IR/GlobalValue.h"
> #include "llvm/IR/Type.h"
> #include "llvm/IR/Value.h"
> +#include "llvm/MC/MCContext.h"
> #include "llvm/MC/MCRegisterInfo.h"
> #include "llvm/Support/Casting.h"
> #include "llvm/Support/CodeGen.h"
> @@ -91,6 +92,8 @@ NoZeroDivCheck("mno-check-zero-division"
> cl::desc("MIPS: Don't trap on integer division by zero."),
> cl::init(false));
>
> +extern cl::opt<bool> EmitJalrReloc;
> +
> static const MCPhysReg Mips64DPRegs[8] = {
> Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
> Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
> @@ -2879,6 +2882,54 @@ getOpndList(SmallVectorImpl<SDValue> &Op
> Ops.push_back(InFlag);
> }
>
> +void MipsTargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
> + SDNode *Node) const {
> + switch (MI.getOpcode()) {
> + default:
> + return;
> + case Mips::JALR:
> + case Mips::JALRPseudo:
> + case Mips::JALR64:
> + case Mips::JALR64Pseudo:
> + case Mips::JALR16_MM:
> + case Mips::JALRC16_MMR6:
> + case Mips::TAILCALLREG:
> + case Mips::TAILCALLREG64:
> + case Mips::TAILCALLR6REG:
> + case Mips::TAILCALL64R6REG:
> + case Mips::TAILCALLREG_MM:
> + case Mips::TAILCALLREG_MMR6: {
> + if (!EmitJalrReloc ||
> + Subtarget.inMips16Mode() ||
> + !isPositionIndependent() ||
> + Node->getNumOperands() < 1 ||
> + Node->getOperand(0).getNumOperands() < 2) {
> + return;
> + }
> + // We are after the callee address, set by LowerCall().
> + // If added to MI, asm printer will emit .reloc R_MIPS_JALR for the
> + // symbol.
> + const SDValue TargetAddr = Node->getOperand(0).getOperand(1);
> + StringRef Sym;
> + if (const GlobalAddressSDNode *G =
> + dyn_cast_or_null<const GlobalAddressSDNode>(TargetAddr)) {
> + Sym = G->getGlobal()->getName();
> + }
> + else if (const ExternalSymbolSDNode *ES =
> + dyn_cast_or_null<const ExternalSymbolSDNode>(TargetAddr)) {
> + Sym = ES->getSymbol();
> + }
> +
> + if (Sym.empty())
> + return;
> +
> + MachineFunction *MF = MI.getParent()->getParent();
> + MCSymbol *S = MF->getContext().getOrCreateSymbol(Sym);
> + MI.addOperand(MachineOperand::CreateMCSymbol(S, MipsII::MO_JALR));
> + }
> + }
> +}
> +
> /// LowerCall - functions arguments are copied from virtual regs to
> /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
> SDValue
> @@ -2930,7 +2981,7 @@ MipsTargetLowering::LowerCall(TargetLowe
> // the maximum out going argument area (including the reserved area), and
> // preallocates the stack space on entrance to the caller.
> //
> - // FIXME: We should do the same for efficency and space.
> + // FIXME: We should do the same for efficiency and space.
>
> // Note: The check on the calling convention below must match
> // MipsABIInfo::GetCalleeAllocdArgSizeInBytes().
>
> Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.h?rev=351485&r1=351484&r2=351485&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsISelLowering.h (original)
> +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.h Thu Jan 17 13:50:37 2019
> @@ -341,6 +341,9 @@ class TargetRegisterClass;
> EmitInstrWithCustomInserter(MachineInstr &MI,
> MachineBasicBlock *MBB) const override;
>
> + void AdjustInstrPostInstrSelection(MachineInstr &MI,
> + SDNode *Node) const override;
> +
> void HandleByVal(CCState *, unsigned &, unsigned) const override;
>
> unsigned getRegisterByName(const char* RegName, EVT VT,
>
> Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=351485&r1=351484&r2=351485&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Thu Jan 17 13:50:37 2019
> @@ -653,6 +653,16 @@ MipsInstrInfo::genInstrWithNewOpc(unsign
>
> MIB.addImm(0);
>
> + // If I has an MCSymbol operand (used by asm printer, to emit R_MIPS_JALR),
> + // add it to the new instruction.
> + for (unsigned J = I->getDesc().getNumOperands(), E = I->getNumOperands();
> + J < E; ++J) {
> + const MachineOperand &MO = I->getOperand(J);
> + if (MO.isMCSymbol() && (MO.getTargetFlags() & MipsII::MO_JALR))
> + MIB.addSym(MO.getMCSymbol(), MipsII::MO_JALR);
> + }
> +
> +
> } else {
> for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {
> if (BranchWithZeroOperand && (unsigned)ZeroOperandPosition == J)
> @@ -825,7 +835,8 @@ MipsInstrInfo::getSerializableDirectMach
> {MO_GOT_HI16, "mips-got-hi16"},
> {MO_GOT_LO16, "mips-got-lo16"},
> {MO_CALL_HI16, "mips-call-hi16"},
> - {MO_CALL_LO16, "mips-call-lo16"}
> + {MO_CALL_LO16, "mips-call-lo16"},
> + {MO_JALR, "mips-jalr"}
> };
> return makeArrayRef(Flags);
> }
>
> Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=351485&r1=351484&r2=351485&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Thu Jan 17 13:50:37 2019
> @@ -1623,11 +1623,15 @@ let isCall=1, hasDelaySlot=1, isCTI=1, D
> class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
> Register RetReg, RegisterOperand ResRO = RO>:
> PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], II_JALR>,
> - PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
> + PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)> {
> + let hasPostISelHook = 1;
> + }
>
> class JumpLinkReg<string opstr, RegisterOperand RO>:
> InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
> - [], II_JALR, FrmR, opstr>;
> + [], II_JALR, FrmR, opstr> {
> + let hasPostISelHook = 1;
> + }
>
> class BGEZAL_FT<string opstr, DAGOperand opnd,
> RegisterOperand RO> :
> @@ -1646,7 +1650,9 @@ let isCall = 1, isTerminator = 1, isRetu
>
> class TailCallReg<Instruction JumpInst, RegisterOperand RO> :
> PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], II_JR>,
> - PseudoInstExpansion<(JumpInst RO:$rs)>;
> + PseudoInstExpansion<(JumpInst RO:$rs)> {
> + let hasPostISelHook = 1;
> + }
> }
>
> class BAL_BR_Pseudo<Instruction RealInst, DAGOperand opnd> :
>
> Modified: llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp?rev=351485&r1=351484&r2=351485&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp Thu Jan 17 13:50:37 2019
> @@ -117,6 +117,8 @@ MCOperand MipsMCInstLower::LowerSymbolOp
> case MipsII::MO_CALL_LO16:
> TargetKind = MipsMCExpr::MEK_CALL_LO16;
> break;
> + case MipsII::MO_JALR:
> + return MCOperand();
> }
>
> switch (MOTy) {
>
> Modified: llvm/trunk/test/CodeGen/Mips/cconv/vector.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/cconv/vector.ll?rev=351485&r1=351484&r2=351485&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/cconv/vector.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/cconv/vector.ll Thu Jan 17 13:50:37 2019
> @@ -1,12 +1,12 @@
> ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
> ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32 -disable-mips-delay-filler | FileCheck %s --check-prefixes=ALL,MIPS32,MIPS32EB
> -; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -relocation-model=pic -mcpu=mips64 -disable-mips-delay-filler | FileCheck %s --check-prefixes=ALL,MIPS64,MIPS64EB
> +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -relocation-model=pic -mcpu=mips64 -disable-mips-delay-filler -mips-jalr-reloc=false | FileCheck %s --check-prefixes=ALL,MIPS64,MIPS64EB
> ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r5 -mattr=+fp64,+msa -disable-mips-delay-filler | FileCheck %s --check-prefixes=ALL,MIPS32R5,MIPS32R5EB
> -; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -relocation-model=pic -mcpu=mips64r5 -mattr=+fp64,+msa -disable-mips-delay-filler | FileCheck %s --check-prefixes=ALL,MIPS64R5,MIPS64R5EB
> +; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -relocation-model=pic -mcpu=mips64r5 -mattr=+fp64,+msa -disable-mips-delay-filler -mips-jalr-reloc=false | FileCheck %s --check-prefixes=ALL,MIPS64R5,MIPS64R5EB
> ; RUN: llc < %s -mtriple=mipsel-unknown-linux-gnu -mcpu=mips32 -disable-mips-delay-filler | FileCheck %s --check-prefixes=ALL,MIPS32,MIPS32EL
> -; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnu -relocation-model=pic -mcpu=mips64 -disable-mips-delay-filler | FileCheck %s --check-prefixes=ALL,MIPS64,MIPS64EL
> +; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnu -relocation-model=pic -mcpu=mips64 -disable-mips-delay-filler -mips-jalr-reloc=false | FileCheck %s --check-prefixes=ALL,MIPS64,MIPS64EL
> ; RUN: llc < %s -mtriple=mipsel-unknown-linux-gnu -mcpu=mips32r5 -mattr=+fp64,+msa -disable-mips-delay-filler | FileCheck %s --check-prefixes=ALL,MIPS32R5,MIPS32R5EL
> -; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnu -relocation-model=pic -mcpu=mips64r5 -mattr=+fp64,+msa -disable-mips-delay-filler | FileCheck %s --check-prefixes=ALL,MIPS64R5,MIPS64R5EL
> +; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnu -relocation-model=pic -mcpu=mips64r5 -mattr=+fp64,+msa -disable-mips-delay-filler -mips-jalr-reloc=false | FileCheck %s --check-prefixes=ALL,MIPS64R5,MIPS64R5EL
>
> ; Test that vector types are passed through the integer register set whether or
> ; not MSA is enabled. This is a ABI requirement for MIPS. For GCC compatibility
>
> Modified: llvm/trunk/test/CodeGen/Mips/gprestore.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/gprestore.ll?rev=351485&r1=351484&r2=351485&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/gprestore.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/gprestore.ll Thu Jan 17 13:50:37 2019
> @@ -1,10 +1,10 @@
> ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
> -; RUN: llc -mtriple=mips-mti-linux-gnu < %s -relocation-model=pic | FileCheck %s --check-prefix=O32
> -; RUN: llc -mtriple=mips64-mti-linux-gnu < %s -relocation-model=pic | FileCheck %s --check-prefix=N64
> -; RUN: llc -mtriple=mips64-mti-linux-gnu < %s -relocation-model=pic -target-abi n32 | FileCheck %s --check-prefix=N32
> -; RUN: llc -mtriple=mips-mti-linux-gnu < %s -relocation-model=pic -O3 | FileCheck %s --check-prefix=O3O32
> -; RUN: llc -mtriple=mips64-mti-linux-gnu < %s -relocation-model=pic -O3 | FileCheck %s --check-prefix=O3N64
> -; RUN: llc -mtriple=mips64-mti-linux-gnu < %s -relocation-model=pic -target-abi n32 -O3 | FileCheck %s --check-prefix=O3N32
> +; RUN: llc -mtriple=mips-mti-linux-gnu < %s -relocation-model=pic -mips-jalr-reloc=false | FileCheck %s --check-prefix=O32
> +; RUN: llc -mtriple=mips64-mti-linux-gnu < %s -relocation-model=pic -mips-jalr-reloc=false | FileCheck %s --check-prefix=N64
> +; RUN: llc -mtriple=mips64-mti-linux-gnu < %s -relocation-model=pic -target-abi n32 -mips-jalr-reloc=false | FileCheck %s --check-prefix=N32
> +; RUN: llc -mtriple=mips-mti-linux-gnu < %s -relocation-model=pic -O3 -mips-jalr-reloc=false | FileCheck %s --check-prefix=O3O32
> +; RUN: llc -mtriple=mips64-mti-linux-gnu < %s -relocation-model=pic -O3 -mips-jalr-reloc=false | FileCheck %s --check-prefix=O3N64
> +; RUN: llc -mtriple=mips64-mti-linux-gnu < %s -relocation-model=pic -target-abi n32 -O3 -mips-jalr-reloc=false | FileCheck %s --check-prefix=O3N32
>
> ; Test that PIC calls use the $25 register. This is an ABI requirement.
>
>
> Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/sdiv.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/sdiv.ll?rev=351485&r1=351484&r2=351485&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/llvm-ir/sdiv.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/llvm-ir/sdiv.ll Thu Jan 17 13:50:37 2019
> @@ -1,36 +1,38 @@
> ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
> ; RUN: llc < %s -mtriple=mips -mcpu=mips2 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefixes=GP32,GP32R0R2
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32,GP32R0R2
> ; RUN: llc < %s -mtriple=mips -mcpu=mips32 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefixes=GP32,GP32R0R2
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32,GP32R0R2
> ; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefixes=GP32,GP32R2R5
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32,GP32R2R5
> ; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefixes=GP32,GP32R2R5
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32,GP32R2R5
> ; RUN: llc < %s -mtriple=mips -mcpu=mips32r5 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefixes=GP32,GP32R2R5
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32,GP32R2R5
> ; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefix=GP32R6
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefix=GP32R6
>
> ; RUN: llc < %s -mtriple=mips64 -mcpu=mips3 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefixes=GP64,GP64R0R1
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64,GP64R0R1
> ; RUN: llc < %s -mtriple=mips64 -mcpu=mips4 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefixes=GP64,GP64R0R1
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64,GP64R0R1
> ; RUN: llc < %s -mtriple=mips64 -mcpu=mips64 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefixes=GP64,GP64R0R1
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64,GP64R0R1
> ; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r2 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefixes=GP64,GP64R2R5
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64,GP64R2R5
> ; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r3 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefixes=GP64,GP64R2R5
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64,GP64R2R5
> ; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r5 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefixes=GP64,GP64R2R5
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64,GP64R2R5
> ; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r6 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefix=GP64R6
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefix=GP64R6
>
> -; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefix=MMR3
> -; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefix=MMR6
> +; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 -mattr=+micromips \
> +; RUN: -relocation-model=pic -mips-jalr-reloc=false | \
> +; RUN: FileCheck %s -check-prefix=MMR3
> +; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -mattr=+micromips \
> +; RUN: -relocation-model=pic -mips-jalr-reloc=false | \
> +; RUN: FileCheck %s -check-prefix=MMR6
>
> define signext i1 @sdiv_i1(i1 signext %a, i1 signext %b) {
> ; GP32-LABEL: sdiv_i1:
>
> Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/srem.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/srem.ll?rev=351485&r1=351484&r2=351485&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/llvm-ir/srem.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/llvm-ir/srem.ll Thu Jan 17 13:50:37 2019
> @@ -1,36 +1,38 @@
> ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
> ; RUN: llc < %s -mtriple=mips -mcpu=mips2 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefixes=GP32,GP32R0R2
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32,GP32R0R2
> ; RUN: llc < %s -mtriple=mips -mcpu=mips32 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefixes=GP32,GP32R0R2
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32,GP32R0R2
> ; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefixes=GP32,GP32R2R5
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32,GP32R2R5
> ; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefixes=GP32,GP32R2R5
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32,GP32R2R5
> ; RUN: llc < %s -mtriple=mips -mcpu=mips32r5 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefixes=GP32,GP32R2R5
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32,GP32R2R5
> ; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefix=GP32R6
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefix=GP32R6
>
> ; RUN: llc < %s -mtriple=mips64 -mcpu=mips3 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefixes=GP64,GP64R0R1
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64,GP64R0R1
> ; RUN: llc < %s -mtriple=mips64 -mcpu=mips4 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefixes=GP64,GP64R0R1
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64,GP64R0R1
> ; RUN: llc < %s -mtriple=mips64 -mcpu=mips64 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefixes=GP64,GP64R0R1
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64,GP64R0R1
> ; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r2 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefixes=GP64,GP64R2R5
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64,GP64R2R5
> ; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r3 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefixes=GP64,GP64R2R5
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64,GP64R2R5
> ; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r5 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefixes=GP64,GP64R2R5
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64,GP64R2R5
> ; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r6 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefix=GP64R6
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefix=GP64R6
>
> -; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefix=MMR3
> -; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefix=MMR6
> +; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 -mattr=+micromips \
> +; RUN: -relocation-model=pic -mips-jalr-reloc=false | \
> +; RUN: FileCheck %s -check-prefix=MMR3
> +; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -mattr=+micromips \
> +; RUN: -relocation-model=pic -mips-jalr-reloc=false | \
> +; RUN: FileCheck %s -check-prefix=MMR6
>
> define signext i1 @srem_i1(i1 signext %a, i1 signext %b) {
> ; GP32-LABEL: srem_i1:
>
> Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/udiv.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/udiv.ll?rev=351485&r1=351484&r2=351485&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/llvm-ir/udiv.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/llvm-ir/udiv.ll Thu Jan 17 13:50:37 2019
> @@ -1,36 +1,38 @@
> ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
> ; RUN: llc < %s -mtriple=mips -mcpu=mips2 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefixes=GP32,GP32R0R1
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32,GP32R0R1
> ; RUN: llc < %s -mtriple=mips -mcpu=mips32 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefixes=GP32,GP32R0R1
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32,GP32R0R1
> ; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefixes=GP32,GP32R2R5
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32,GP32R2R5
> ; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefixes=GP32,GP32R2R5
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32,GP32R2R5
> ; RUN: llc < %s -mtriple=mips -mcpu=mips32r5 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefixes=GP32,GP32R2R5
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32,GP32R2R5
> ; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefix=GP32R6
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefix=GP32R6
>
> ; RUN: llc < %s -mtriple=mips64 -mcpu=mips3 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefixes=GP64,GP64R0R1
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64,GP64R0R1
> ; RUN: llc < %s -mtriple=mips64 -mcpu=mips4 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefixes=GP64,GP64R0R1
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64,GP64R0R1
> ; RUN: llc < %s -mtriple=mips64 -mcpu=mips64 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefixes=GP64,GP64R0R2
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64,GP64R0R2
> ; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r2 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefixes=GP64,GP64R2R5
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64,GP64R2R5
> ; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r3 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefixes=GP64,GP64R2R5
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64,GP64R2R5
> ; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r5 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefixes=GP64,GP64R2R5
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64,GP64R2R5
> ; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r6 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefix=GP64R6
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefix=GP64R6
>
> -; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefix=MMR3
> -; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefix=MMR6
> +; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 -mattr=+micromips \
> +; RUN: -relocation-model=pic -mips-jalr-reloc=false | \
> +; RUN: FileCheck %s -check-prefix=MMR3
> +; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -mattr=+micromips \
> +; RUN: -relocation-model=pic -mips-jalr-reloc=false | \
> +; RUN: FileCheck %s -check-prefix=MMR6
>
> define zeroext i1 @udiv_i1(i1 zeroext %a, i1 zeroext %b) {
> ; GP32-LABEL: udiv_i1:
>
> Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/urem.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/urem.ll?rev=351485&r1=351484&r2=351485&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/llvm-ir/urem.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/llvm-ir/urem.ll Thu Jan 17 13:50:37 2019
> @@ -1,36 +1,38 @@
> ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
> ; RUN: llc < %s -mtriple=mips -mcpu=mips2 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefixes=GP32,GP32R0R2
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32,GP32R0R2
> ; RUN: llc < %s -mtriple=mips -mcpu=mips32 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefixes=GP32,GP32R0R2
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32,GP32R0R2
> ; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefixes=GP32,GP32R2R5
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32,GP32R2R5
> ; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefixes=GP32,GP32R2R5
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32,GP32R2R5
> ; RUN: llc < %s -mtriple=mips -mcpu=mips32r5 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefixes=GP32,GP32R2R5
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32,GP32R2R5
> ; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefix=GP32R6
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefix=GP32R6
>
> ; RUN: llc < %s -mtriple=mips64 -mcpu=mips3 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefixes=GP64,GP64R0R1
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64,GP64R0R1
> ; RUN: llc < %s -mtriple=mips64 -mcpu=mips4 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefixes=GP64,GP64R0R1
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64,GP64R0R1
> ; RUN: llc < %s -mtriple=mips64 -mcpu=mips64 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefixes=GP64,GP64R0R1
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64,GP64R0R1
> ; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r2 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefixes=GP64,GP64R2R5
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64,GP64R2R5
> ; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r3 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefixes=GP64,GP64R2R5
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64,GP64R2R5
> ; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r5 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefixes=GP64,GP64R2R5
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64,GP64R2R5
> ; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r6 -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefix=GP64R6
> +; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefix=GP64R6
>
> -; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefix=MMR3
> -; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic \
> -; RUN: | FileCheck %s -check-prefix=MMR6
> +; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 -mattr=+micromips \
> +; RUN: -relocation-model=pic -mips-jalr-reloc=false | \
> +; RUN: FileCheck %s -check-prefix=MMR3
> +; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -mattr=+micromips \
> +; RUN: -relocation-model=pic -mips-jalr-reloc=false | \
> +; RUN: FileCheck %s -check-prefix=MMR6
>
> define signext i1 @urem_i1(i1 signext %a, i1 signext %b) {
> ; GP32-LABEL: urem_i1:
>
> Modified: llvm/trunk/test/CodeGen/Mips/long-call-attr.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/long-call-attr.ll?rev=351485&r1=351484&r2=351485&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/long-call-attr.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/long-call-attr.ll Thu Jan 17 13:50:37 2019
> @@ -1,11 +1,11 @@
> ; RUN: llc -march=mips -target-abi o32 --mattr=+long-calls,+noabicalls < %s \
> -; RUN: | FileCheck -check-prefix=O32 %s
> +; RUN: -mips-jalr-reloc=false | FileCheck -check-prefix=O32 %s
> ; RUN: llc -march=mips -target-abi o32 --mattr=-long-calls,+noabicalls < %s \
> -; RUN: | FileCheck -check-prefix=O32 %s
> +; RUN: -mips-jalr-reloc=false | FileCheck -check-prefix=O32 %s
> ; RUN: llc -march=mips64 -target-abi n64 --mattr=+long-calls,+noabicalls < %s \
> -; RUN: | FileCheck -check-prefix=N64 %s
> +; RUN: -mips-jalr-reloc=false | FileCheck -check-prefix=N64 %s
> ; RUN: llc -march=mips64 -target-abi n64 --mattr=-long-calls,+noabicalls < %s \
> -; RUN: | FileCheck -check-prefix=N64 %s
> +; RUN: -mips-jalr-reloc=false | FileCheck -check-prefix=N64 %s
>
> declare void @far() #0
>
>
> Modified: llvm/trunk/test/CodeGen/Mips/long-call-mcount.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/long-call-mcount.ll?rev=351485&r1=351484&r2=351485&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/long-call-mcount.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/long-call-mcount.ll Thu Jan 17 13:50:37 2019
> @@ -1,8 +1,8 @@
> ; Check call to mcount in case of long/short call options.
> ; RUN: llc -march=mips -target-abi o32 --mattr=+long-calls,+noabicalls < %s \
> -; RUN: | FileCheck -check-prefixes=CHECK,LONG %s
> +; RUN: -mips-jalr-reloc=false | FileCheck -check-prefixes=CHECK,LONG %s
> ; RUN: llc -march=mips -target-abi o32 --mattr=-long-calls,+noabicalls < %s \
> -; RUN: | FileCheck -check-prefixes=CHECK,SHORT %s
> +; RUN: -mips-jalr-reloc=false | FileCheck -check-prefixes=CHECK,SHORT %s
>
> ; Function Attrs: noinline nounwind optnone
> define void @foo() #0 {
>
> Modified: llvm/trunk/test/CodeGen/Mips/msa/f16-llvm-ir.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/f16-llvm-ir.ll?rev=351485&r1=351484&r2=351485&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/msa/f16-llvm-ir.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/msa/f16-llvm-ir.ll Thu Jan 17 13:50:37 2019
> @@ -1,22 +1,22 @@
> ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
> ; RUN: llc -relocation-model=pic -mtriple=mipsel-- -mcpu=mips32r5 \
> -; RUN: -mattr=+fp64,+msa -verify-machineinstrs < %s | FileCheck %s \
> +; RUN: -mattr=+fp64,+msa -verify-machineinstrs -mips-jalr-reloc=false < %s | FileCheck %s \
> ; RUN: --check-prefixes=ALL,MIPS32,MIPSR5,MIPS32-O32,MIPS32R5-O32
> ; RUN: llc -relocation-model=pic -mtriple=mips64el-- -mcpu=mips64r5 \
> -; RUN: -mattr=+fp64,+msa -verify-machineinstrs -target-abi n32 < %s | FileCheck %s \
> +; RUN: -mattr=+fp64,+msa -verify-machineinstrs -target-abi n32 -mips-jalr-reloc=false < %s | FileCheck %s \
> ; RUN: --check-prefixes=ALL,MIPS64,MIPSR5,MIPS64-N32,MIPS64R5-N32
> ; RUN: llc -relocation-model=pic -mtriple=mips64el-- -mcpu=mips64r5 \
> -; RUN: -mattr=+fp64,+msa -verify-machineinstrs -target-abi n64 < %s | FileCheck %s \
> +; RUN: -mattr=+fp64,+msa -verify-machineinstrs -target-abi n64 -mips-jalr-reloc=false < %s | FileCheck %s \
> ; RUN: --check-prefixes=ALL,MIPS64,MIPSR5,MIPS64-N64,MIPS64R5-N64
>
> ; RUN: llc -relocation-model=pic -mtriple=mipsel-- -mcpu=mips32r6 \
> -; RUN: -mattr=+fp64,+msa -verify-machineinstrs < %s | FileCheck %s \
> +; RUN: -mattr=+fp64,+msa -verify-machineinstrs -mips-jalr-reloc=false < %s | FileCheck %s \
> ; RUN: --check-prefixes=ALL,MIPS32,MIPSR6,MIPSR6-O32
> ; RUN: llc -relocation-model=pic -mtriple=mips64el-- -mcpu=mips64r6 \
> -; RUN: -mattr=+fp64,+msa -verify-machineinstrs -target-abi n32 < %s | FileCheck %s \
> +; RUN: -mattr=+fp64,+msa -verify-machineinstrs -target-abi n32 -mips-jalr-reloc=false < %s | FileCheck %s \
> ; RUN: --check-prefixes=ALL,MIPS64,MIPSR6,MIPS64-N32,MIPSR6-N32
> ; RUN: llc -relocation-model=pic -mtriple=mips64el-- -mcpu=mips64r6 \
> -; RUN: -mattr=+fp64,+msa -verify-machineinstrs -target-abi n64 < %s | FileCheck %s \
> +; RUN: -mattr=+fp64,+msa -verify-machineinstrs -target-abi n64 -mips-jalr-reloc=false < %s | FileCheck %s \
> ; RUN: --check-prefixes=ALL,MIPS64,MIPSR6,MIPS64-N64,MIPSR6-N64
>
>
>
> Modified: llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll?rev=351485&r1=351484&r2=351485&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll Thu Jan 17 13:50:37 2019
> @@ -1,5 +1,6 @@
> ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
> -; RUN: llc -mtriple=mipsel-unknown-linux-gnu -relocation-model=pic < %s | FileCheck %s
> +; RUN: llc -mtriple=mipsel-unknown-linux-gnu -relocation-model=pic \
> +; RUN: -mips-jalr-reloc=false < %s | FileCheck %s
>
> %0 = type { i8, i16, i32, i64, double, i32, [4 x i8] }
> %struct.S1 = type { i8, i16, i32, i64, double, i32 }
>
> Added: llvm/trunk/test/CodeGen/Mips/reloc-jalr.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/reloc-jalr.ll?rev=351485&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/reloc-jalr.ll (added)
> +++ llvm/trunk/test/CodeGen/Mips/reloc-jalr.ll Thu Jan 17 13:50:37 2019
> @@ -0,0 +1,154 @@
> +; RUN: llc -mtriple=mips-linux-gnu -relocation-model=pic -mips-tail-calls=1 \
> +; RUN: -O2 < %s | \
> +; RUN: FileCheck %s -check-prefixes=ALL,JALR-32R2,TAILCALL-32R2
> +
> +; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=pic -mips-tail-calls=1 \
> +; RUN: -O2 < %s | \
> +; RUN: FileCheck %s -check-prefixes=ALL,JALR-64R2,TAILCALL-64R2
> +
> +; RUN: llc -mtriple=mips-linux-gnu -relocation-model=pic -mips-tail-calls=1 \
> +; RUN: -O2 -mcpu=mips32r6 -mips-compact-branches=always < %s | \
> +; RUN: FileCheck %s -check-prefixes=ALL,JALR-32R6,TAILCALL-32R6
> +
> +; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=pic -mips-tail-calls=1 \
> +; RUN: -O2 -mcpu=mips64r6 -mips-compact-branches=always < %s | \
> +; RUN: FileCheck %s -check-prefixes=ALL,JALR-64R6,TAILCALL-64R6
> +
> +; RUN: llc -mtriple=mips-linux-gnu -relocation-model=pic -mips-tail-calls=1 \
> +; RUN: -O2 -mcpu=mips32r6 -mips-compact-branches=never < %s | \
> +; RUN: FileCheck %s -check-prefixes=ALL,JALR-32R2,TAILCALL-32R2
> +
> +; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=pic -mips-tail-calls=1 \
> +; RUN: -O2 -mcpu=mips64r6 -mips-compact-branches=never < %s | \
> +; RUN: FileCheck %s -check-prefixes=ALL,JALR-64R2,TAILCALL-64R2
> +
> +; RUN: llc -mtriple=mips-linux-gnu -relocation-model=pic -mips-tail-calls=1 \
> +; RUN: -O2 -mattr=+micromips -mcpu=mips32r2 < %s | \
> +; RUN: FileCheck %s -check-prefixes=ALL,JALR-MM,TAILCALL-MM
> +
> +; RUN: llc -mtriple=mips-linux-gnu -relocation-model=pic -mips-tail-calls=1 \
> +; RUN: -O2 -mattr=+micromips -mcpu=mips32r6 < %s | \
> +; RUN: FileCheck %s -check-prefixes=ALL,JALR-MM
> +
> +; RUN: llc -mtriple=mips-linux-gnu -relocation-model=pic \
> +; RUN: -O0 < %s | FileCheck %s -check-prefixes=ALL,JALR-32R2
> +
> +; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=pic \
> +; RUN: -O0 < %s | FileCheck %s -check-prefixes=ALL,JALR-64R2
> +
> +; RUN: llc -mtriple=mips-linux-gnu -relocation-model=pic \
> +; RUN: -O0 -mcpu=mips32r6 -mips-compact-branches=always < %s | \
> +; RUN: FileCheck %s -check-prefixes=ALL,JALR-32R6
> +
> +; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=pic \
> +; RUN: -O0 -mcpu=mips64r6 -mips-compact-branches=always < %s | \
> +; RUN: FileCheck %s -check-prefixes=ALL,JALR-64R6
> +
> +; RUN: llc -mtriple=mips-linux-gnu -relocation-model=pic \
> +; RUN: -O0 -mcpu=mips32r6 -mips-compact-branches=never < %s | \
> +; RUN: FileCheck %s -check-prefixes=ALL,JALR-32R2
> +
> +; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=pic \
> +; RUN: -O0 -mcpu=mips64r6 -mips-compact-branches=never < %s | \
> +; RUN: FileCheck %s -check-prefixes=ALL,JALR-64R2
> +
> +; RUN: llc -mtriple=mips-linux-gnu -relocation-model=pic \
> +; RUN: -O0 -mattr=+micromips -mcpu=mips32r2 < %s | \
> +; RUN: FileCheck %s -check-prefixes=ALL,JALR-MM
> +
> +; RUN: llc -mtriple=mips-linux-gnu -relocation-model=pic \
> +; RUN: -O0 -mattr=+micromips -mcpu=mips32r6 < %s | \
> +; RUN: FileCheck %s -check-prefixes=ALL,JALR-MM
> +
> +; RUN: llc -mtriple=mips-linux-gnu -relocation-model=pic -mips-tail-calls=1 \
> +; RUN: -O2 -mips-jalr-reloc=false < %s | \
> +; RUN: FileCheck %s -check-prefixes=ALL,NORELOC
> +
> +; RUN: llc -mtriple=mips-linux-gnu -relocation-model=static -mips-tail-calls=1 \
> +; RUN: -O2 < %s | \
> +; RUN: FileCheck %s -check-prefixes=ALL,NORELOC
> +
> +; RUN: llc -mtriple=mips-linux-gnu -relocation-model=pic -mips-tail-calls=1 \
> +; RUN: -O0 -mips-jalr-reloc=false < %s | \
> +; RUN: FileCheck %s -check-prefixes=ALL,NORELOC
> +
> +; RUN: llc -mtriple=mips-linux-gnu -relocation-model=static -mips-tail-calls=1 \
> +; RUN: -O0 < %s | \
> +; RUN: FileCheck %s -check-prefixes=ALL,NORELOC
> +
> +; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=pic -mips-tail-calls=1 \
> +; RUN: -O2 -mips-jalr-reloc=false < %s | \
> +; RUN: FileCheck %s -check-prefixes=ALL,NORELOC
> +
> +; RUN: llc -mtriple=mips64-linux-gnu -mips-tail-calls=1 \
> +; RUN: -O2 -relocation-model=static < %s | \
> +; RUN: FileCheck %s -check-prefixes=ALL,NORELOC
> +
> +; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=pic \
> +; RUN: -O0 -mips-jalr-reloc=false < %s | \
> +; RUN: FileCheck %s -check-prefixes=ALL,NORELOC
> +
> +; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static \
> +; RUN: -O0 < %s | \
> +; RUN: FileCheck %s -check-prefixes=ALL,NORELOC
> +
> +define internal void @foo() noinline {
> +entry:
> + ret void
> +}
> +
> +define void @checkCall() {
> +entry:
> +; ALL-LABEL: checkCall:
> + call void @foo()
> +; JALR-32R2: .reloc ([[TMPLABEL:.*]]), R_MIPS_JALR, foo
> +; JALR-32R2-NEXT: [[TMPLABEL]]:
> +; JALR-32R2-NEXT: jalr $25
> +
> +; JALR-64R2: .reloc [[TMPLABEL:.*]], R_MIPS_JALR, foo
> +; JALR-64R2-NEXT: [[TMPLABEL]]:
> +; JALR-64R2-NEXT: jalr $25
> +
> +; JALR-MM: .reloc ([[TMPLABEL:.*]]), R_MICROMIPS_JALR, foo
> +; JALR-MM-NEXT: [[TMPLABEL]]:
> +; JALR-MM-NEXT: jalr $25
> +
> +; JALR-32R6: .reloc ([[TMPLABEL:.*]]), R_MIPS_JALR, foo
> +; JALR-32R6-NEXT: [[TMPLABEL]]:
> +; JALR-32R6-NEXT: jalrc $25
> +
> +; JALR-64R6: .reloc [[TMPLABEL:.*]], R_MIPS_JALR, foo
> +; JALR-64R6-NEXT: [[TMPLABEL]]:
> +; JALR-64R6-NEXT: jalrc $25
> +
> +; NORELOC-NOT: R_MIPS_JALR
> + ret void
> +}
> +
> +define void @checkTailCall() {
> +entry:
> +; ALL-LABEL: checkTailCall:
> + tail call void @foo()
> +; TAILCALL-32R2: .reloc ([[TMPLABEL:.*]]), R_MIPS_JALR, foo
> +; TAILCALL-32R2-NEXT: [[TMPLABEL]]:
> +; TAILCALL-32R2-NEXT: jr $25
> +
> +; TAILCALL-64R2: .reloc [[TMPLABEL:.*]], R_MIPS_JALR, foo
> +; TAILCALL-64R2-NEXT: [[TMPLABEL]]:
> +; TAILCALL-64R2-NEXT: jr $25
> +
> +; TAILCALL-MM: .reloc ([[TMPLABEL:.*]]), R_MICROMIPS_JALR, foo
> +; TAILCALL-MM-NEXT: [[TMPLABEL]]:
> +; TAILCALL-MM-NEXT: jrc $25
> +
> +; TAILCALL-32R6: .reloc ([[TMPLABEL:.*]]), R_MIPS_JALR, foo
> +; TAILCALL-32R6-NEXT: [[TMPLABEL]]:
> +; TAILCALL-32R6-NEXT: jrc $25
> +
> +; TAILCALL-64R6: .reloc [[TMPLABEL:.*]], R_MIPS_JALR, foo
> +; TAILCALL-64R6-NEXT: [[TMPLABEL]]:
> +; TAILCALL-64R6-NEXT: jrc $25
> +
> +; NORELOC-NOT: R_MIPS_JALR
> + ret void
> +}
>
> Modified: llvm/trunk/test/CodeGen/Mips/shrink-wrapping.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/shrink-wrapping.ll?rev=351485&r1=351484&r2=351485&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/shrink-wrapping.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/shrink-wrapping.ll Thu Jan 17 13:50:37 2019
> @@ -9,11 +9,11 @@
> ; RUN: FileCheck %s -check-prefix=NO-SHRINK-WRAP-STATIC
>
> ; RUN: llc -mtriple=mips-unknown-linux-gnu -enable-shrink-wrap=true \
> -; RUN: -relocation-model=pic < %s | \
> +; RUN: -relocation-model=pic -mips-jalr-reloc=false < %s | \
> ; RUN: FileCheck %s -check-prefix=SHRINK-WRAP-PIC
>
> ; RUN: llc -mtriple=mips-unknown-linux-gnu -enable-shrink-wrap=false \
> -; RUN: -relocation-model=pic < %s | \
> +; RUN: -relocation-model=pic -mips-jalr-reloc=false < %s | \
> ; RUN: FileCheck %s -check-prefix=NO-SHRINK-WRAP-PIC
>
> ; RUN: llc -mtriple=mips64-unknown-linux-gnu -enable-shrink-wrap=true \
> @@ -25,11 +25,11 @@
> ; RUN: FileCheck %s -check-prefix=NO-SHRINK-WRAP-64-STATIC
>
> ; RUN: llc -mtriple=mips64-unknown-linux-gnu -enable-shrink-wrap=true \
> -; RUN: -relocation-model=pic < %s | \
> +; RUN: -relocation-model=pic -mips-jalr-reloc=false < %s | \
> ; RUN: FileCheck %s -check-prefix=SHRINK-WRAP-64-PIC
>
> ; RUN: llc -mtriple=mips64-unknown-linux-gnu -enable-shrink-wrap=false \
> -; RUN: -relocation-model=pic < %s | \
> +; RUN: -relocation-model=pic -mips-jalr-reloc=false < %s | \
> ; RUN: FileCheck %s -check-prefix=NO-SHRINK-WRAP-64-PIC
>
> declare void @f(i32 signext)
>
>
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