[PATCH] D57085: [RISCV] Custom-legalise 32-bit variable shifts on RV64

[Alex Bradbury via Phabricator via llvm-commits]

asb updated this revision to Diff 183254.
asb marked 4 inline comments as done.
asb added a comment.

Update to address review feedback (thanks!). Only a single pattern is needed for each DAG node now thanks to:

- Adding a DAG combine that does SimplifyDemandedBits on the operands (only lower 32-bits of first operand and lower 5 bits of second operand are read). For this purpose, this seems better than implementing SimplifyDemandedBitsForTargetNode as there is no guarantee that would be called (and it's not for e.g. the anyext return test cases)
- Implementing ComputeNumSignBitsForTargetNode


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D57085/new/

https://reviews.llvm.org/D57085

Files:
  lib/Target/RISCV/RISCVISelLowering.cpp
  lib/Target/RISCV/RISCVISelLowering.h
  lib/Target/RISCV/RISCVInstrInfo.td
  test/CodeGen/RISCV/atomic-cmpxchg.ll
  test/CodeGen/RISCV/atomic-rmw.ll
  test/CodeGen/RISCV/pr40333.ll

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