[PATCH] D56526: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI

[Ana Pazos via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL352010: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI (authored by apazos, committed by ).
Herald added subscribers: llvm-commits, jrtc27.

Changed prior to commit:
  https://reviews.llvm.org/D56526?vs=182995&id=183229#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D56526/new/

https://reviews.llvm.org/D56526

Files:
  llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.h
  llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td


Index: llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.cpp
===================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -447,3 +447,16 @@
   }
   }
 }
+
+bool RISCVInstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
+  const unsigned Opcode = MI.getOpcode();
+  switch(Opcode) {
+    default:
+      break;
+    case RISCV::ADDI:
+    case RISCV::ORI:
+    case RISCV::XORI:
+      return (MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == RISCV::X0);
+  }
+  return MI.isAsCheapAsAMove();
+}
Index: llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.h
===================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.h
+++ llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.h
@@ -78,6 +78,8 @@
 
   bool isBranchOffsetInRange(unsigned BranchOpc,
                              int64_t BrOffset) const override;
+
+  bool isAsCheapAsAMove(const MachineInstr &MI) const override;
 };
 }
 #endif
Index: llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td
===================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td
+++ llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td
@@ -312,7 +312,7 @@
 //===----------------------------------------------------------------------===//
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
-let isReMaterializable = 1 in
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in
 def LUI : RVInstU<OPC_LUI, (outs GPR:$rd), (ins uimm20_lui:$imm20),
                   "lui", "$rd, $imm20">;
 
@@ -348,13 +348,13 @@
 
 // ADDI isn't always rematerializable, but isReMaterializable will be used as
 // a hint which is verified in isReallyTriviallyReMaterializable.
-let isReMaterializable = 1 in
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in
 def ADDI  : ALU_ri<0b000, "addi">;
 
 def SLTI  : ALU_ri<0b010, "slti">;
 def SLTIU : ALU_ri<0b011, "sltiu">;
 
-let isReMaterializable = 1 in {
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
 def XORI  : ALU_ri<0b100, "xori">;
 def ORI   : ALU_ri<0b110, "ori">;
 }


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D56526.183229.patch
Type: text/x-patch
Size: 2156 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20190124/e4dece7f/attachment.bin>