[llvm] r352008 - [RISCV] Set isReMaterializable for ORI, XORI

[Ana Pazos via llvm-commits]

Author: apazos
Date: Wed Jan 23 18:31:23 2019
New Revision: 352008

URL: http://llvm.org/viewvc/llvm-project?rev=352008&view=rev
Log:
[RISCV] Set isReMaterializable for ORI, XORI

Reviewers: asb

Reviewed By: asb

Subscribers: asb, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei

Differential Revision: https://reviews.llvm.org/D57069

Modified:
    llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td

Modified: llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td?rev=352008&r1=352007&r2=352008&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td Wed Jan 23 18:31:23 2019
@@ -353,8 +353,12 @@ def ADDI  : ALU_ri<0b000, "addi">;
 
 def SLTI  : ALU_ri<0b010, "slti">;
 def SLTIU : ALU_ri<0b011, "sltiu">;
+
+let isReMaterializable = 1 in {
 def XORI  : ALU_ri<0b100, "xori">;
 def ORI   : ALU_ri<0b110, "ori">;
+}
+
 def ANDI  : ALU_ri<0b111, "andi">;
 
 def SLLI : Shift_ri<0, 0b001, "slli">;