[PATCH] D57085: [RISCV] Custom-legalise 32-bit variable shifts on RV64

[Alex Bradbury via Phabricator via llvm-commits]

asb updated this revision to Diff 183091.
asb added a comment.

Refactored patch slightly in a way that will make it easier to add support for legalising sdiv/udiv/urem in the same way.

Also remove TODO from pr40333.ll


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D57085/new/

https://reviews.llvm.org/D57085

Files:
  lib/Target/RISCV/RISCVISelLowering.cpp
  lib/Target/RISCV/RISCVISelLowering.h
  lib/Target/RISCV/RISCVInstrInfo.td
  test/CodeGen/RISCV/atomic-cmpxchg.ll
  test/CodeGen/RISCV/atomic-rmw.ll
  test/CodeGen/RISCV/pr40333.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D57085.183091.patch
Type: text/x-patch
Size: 53027 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20190123/553d481b/attachment.bin>