[llvm] r351886 - AMDGPU/GlobalISel: Start selectively legalizing 16-bit operations
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 22 14:00:20 PST 2019
Author: arsenm
Date: Tue Jan 22 14:00:19 2019
New Revision: 351886
URL: http://llvm.org/viewvc/llvm-project?rev=351886&view=rev
Log:
AMDGPU/GlobalISel: Start selectively legalizing 16-bit operations
It might be a bit nicer to use the fancy .legalIf and co. predicates,
but this was requiring more boilerplate and disables the coverage
assertions.
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp?rev=351886&r1=351885&r2=351886&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp Tue Jan 22 14:00:19 2019
@@ -274,10 +274,15 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo
.legalFor({{S32, S1}, {S64, S1}, {V2S32, S1}, {V2S16, S1}})
.clampScalar(0, S32, S64);
- getActionDefinitionsBuilder({G_SHL, G_LSHR, G_ASHR})
- .legalFor({{S32, S32}, {S64, S32}})
- .clampScalar(1, S32, S32);
-
+ // TODO: Only the low 4/5/6 bits of the shift amount are observed, so we can
+ // be more flexible with the shift amount type.
+ auto &Shifts = getActionDefinitionsBuilder({G_SHL, G_LSHR, G_ASHR})
+ .legalFor({{S32, S32}, {S64, S32}});
+ if (ST.has16BitInsts())
+ Shifts.legalFor({{S16, S32}, {S16, S16}});
+ else
+ Shifts.clampScalar(0, S32, S64);
+ Shifts.clampScalar(1, S32, S32);
// FIXME: When RegBankSelect inserts copies, it will only create new
// registers with scalar types. This means we can end up with
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir?rev=351886&r1=351885&r2=351886&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir Tue Jan 22 14:00:19 2019
@@ -1,5 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefix=SI %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefix=VI %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX9 %s
---
name: test_ashr_i32_i32
@@ -7,11 +9,21 @@ body: |
bb.0:
liveins: $vgpr0, $vgpr1
- ; CHECK-LABEL: name: test_ashr_i32_i32
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[COPY1]](s32)
- ; CHECK: $vgpr0 = COPY [[ASHR]](s32)
+ ; SI-LABEL: name: test_ashr_i32_i32
+ ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[COPY1]](s32)
+ ; SI: $vgpr0 = COPY [[ASHR]](s32)
+ ; VI-LABEL: name: test_ashr_i32_i32
+ ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; VI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[ASHR]](s32)
+ ; GFX9-LABEL: name: test_ashr_i32_i32
+ ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; GFX9: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[COPY1]](s32)
+ ; GFX9: $vgpr0 = COPY [[ASHR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = G_ASHR %0, %1
@@ -23,12 +35,24 @@ body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
- ; CHECK-LABEL: name: test_ashr_i64_i64
- ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
- ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[TRUNC]](s32)
- ; CHECK: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
+ ; SI-LABEL: name: test_ashr_i64_i64
+ ; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; SI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
+ ; SI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+ ; SI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[TRUNC]](s32)
+ ; SI: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
+ ; VI-LABEL: name: test_ashr_i64_i64
+ ; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; VI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
+ ; VI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+ ; VI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[TRUNC]](s32)
+ ; VI: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
+ ; GFX9-LABEL: name: test_ashr_i64_i64
+ ; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; GFX9: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
+ ; GFX9: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+ ; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[TRUNC]](s32)
+ ; GFX9: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = COPY $vgpr2_vgpr3
%2:_(s64) = G_ASHR %0, %1
@@ -40,11 +64,21 @@ body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2
- ; CHECK-LABEL: name: test_ashr_i64_i32
- ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[COPY1]](s32)
- ; CHECK: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
+ ; SI-LABEL: name: test_ashr_i64_i32
+ ; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
+ ; SI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[COPY1]](s32)
+ ; SI: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
+ ; VI-LABEL: name: test_ashr_i64_i32
+ ; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
+ ; VI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[COPY1]](s32)
+ ; VI: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
+ ; GFX9-LABEL: name: test_ashr_i64_i32
+ ; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
+ ; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[COPY1]](s32)
+ ; GFX9: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
%2:_(s64) = G_ASHR %0, %1
@@ -56,17 +90,163 @@ body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2
- ; CHECK-LABEL: name: test_ashr_i64_i16
- ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[AND]](s32)
- ; CHECK: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
+ ; SI-LABEL: name: test_ashr_i64_i16
+ ; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
+ ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; SI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[AND]](s32)
+ ; SI: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
+ ; VI-LABEL: name: test_ashr_i64_i16
+ ; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
+ ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; VI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[AND]](s32)
+ ; VI: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
+ ; GFX9-LABEL: name: test_ashr_i64_i16
+ ; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
+ ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[AND]](s32)
+ ; GFX9: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
%2:_(s16) = G_TRUNC %1
%3:_(s64) = G_ASHR %0, %2
$vgpr0_vgpr1 = COPY %3
...
+
+---
+name: test_ashr_i16_i32
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+
+ ; SI-LABEL: name: test_ashr_i16_i32
+ ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
+ ; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[COPY1]](s32)
+ ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)
+ ; SI: $vgpr0 = COPY [[COPY3]](s32)
+ ; VI-LABEL: name: test_ashr_i16_i32
+ ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; VI: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC]], [[COPY1]](s32)
+ ; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16)
+ ; VI: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; GFX9-LABEL: name: test_ashr_i16_i32
+ ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC]], [[COPY1]](s32)
+ ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16)
+ ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s16) = G_TRUNC %0
+ %3:_(s16) = G_ASHR %2, %1
+ %4:_(s32) = G_ANYEXT %3
+ $vgpr0 = COPY %4
+...
+
+---
+name: test_ashr_i16_i16
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+
+ ; SI-LABEL: name: test_ashr_i16_i16
+ ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
+ ; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[AND]](s32)
+ ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)
+ ; SI: $vgpr0 = COPY [[COPY4]](s32)
+ ; VI-LABEL: name: test_ashr_i16_i16
+ ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; VI: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC]], [[TRUNC1]](s16)
+ ; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16)
+ ; VI: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; GFX9-LABEL: name: test_ashr_i16_i16
+ ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC]], [[TRUNC1]](s16)
+ ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16)
+ ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s16) = G_TRUNC %0
+ %3:_(s16) = G_TRUNC %1
+ %4:_(s16) = G_ASHR %2, %3
+ %5:_(s32) = G_ANYEXT %4
+ $vgpr0 = COPY %5
+...
+
+---
+name: test_ashr_i16_i8
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+
+ ; SI-LABEL: name: test_ashr_i16_i8
+ ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
+ ; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[AND]](s32)
+ ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)
+ ; SI: $vgpr0 = COPY [[COPY4]](s32)
+ ; VI-LABEL: name: test_ashr_i16_i8
+ ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; VI: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC]], [[AND]](s32)
+ ; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16)
+ ; VI: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; GFX9-LABEL: name: test_ashr_i16_i8
+ ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC]], [[AND]](s32)
+ ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16)
+ ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s16) = G_TRUNC %0
+ %3:_(s8) = G_TRUNC %1
+ %4:_(s16) = G_ASHR %2, %3
+ %5:_(s32) = G_ANYEXT %4
+ $vgpr0 = COPY %5
+...
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir?rev=351886&r1=351885&r2=351886&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir Tue Jan 22 14:00:19 2019
@@ -1,5 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefix=SI %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefix=VI %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX9 %s
---
name: test_lshr_i32_i32
@@ -7,11 +9,21 @@ body: |
bb.0:
liveins: $vgpr0, $vgpr1
- ; CHECK-LABEL: name: test_lshr_i32_i32
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[COPY1]](s32)
- ; CHECK: $vgpr0 = COPY [[LSHR]](s32)
+ ; SI-LABEL: name: test_lshr_i32_i32
+ ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[COPY1]](s32)
+ ; SI: $vgpr0 = COPY [[LSHR]](s32)
+ ; VI-LABEL: name: test_lshr_i32_i32
+ ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[LSHR]](s32)
+ ; GFX9-LABEL: name: test_lshr_i32_i32
+ ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[COPY1]](s32)
+ ; GFX9: $vgpr0 = COPY [[LSHR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = G_LSHR %0, %1
@@ -23,12 +35,24 @@ body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
- ; CHECK-LABEL: name: test_lshr_i64_i64
- ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
- ; CHECK: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[TRUNC]](s32)
- ; CHECK: $vgpr0_vgpr1 = COPY [[LSHR]](s64)
+ ; SI-LABEL: name: test_lshr_i64_i64
+ ; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; SI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
+ ; SI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+ ; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[TRUNC]](s32)
+ ; SI: $vgpr0_vgpr1 = COPY [[LSHR]](s64)
+ ; VI-LABEL: name: test_lshr_i64_i64
+ ; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; VI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
+ ; VI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+ ; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[TRUNC]](s32)
+ ; VI: $vgpr0_vgpr1 = COPY [[LSHR]](s64)
+ ; GFX9-LABEL: name: test_lshr_i64_i64
+ ; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; GFX9: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
+ ; GFX9: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+ ; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[TRUNC]](s32)
+ ; GFX9: $vgpr0_vgpr1 = COPY [[LSHR]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = COPY $vgpr2_vgpr3
%2:_(s64) = G_LSHR %0, %1
@@ -40,11 +64,21 @@ body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2
- ; CHECK-LABEL: name: test_lshr_i64_i32
- ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; CHECK: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[COPY1]](s32)
- ; CHECK: $vgpr0_vgpr1 = COPY [[LSHR]](s64)
+ ; SI-LABEL: name: test_lshr_i64_i32
+ ; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
+ ; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[COPY1]](s32)
+ ; SI: $vgpr0_vgpr1 = COPY [[LSHR]](s64)
+ ; VI-LABEL: name: test_lshr_i64_i32
+ ; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
+ ; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[COPY1]](s32)
+ ; VI: $vgpr0_vgpr1 = COPY [[LSHR]](s64)
+ ; GFX9-LABEL: name: test_lshr_i64_i32
+ ; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
+ ; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[COPY1]](s32)
+ ; GFX9: $vgpr0_vgpr1 = COPY [[LSHR]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
%2:_(s64) = G_LSHR %0, %1
@@ -56,17 +90,160 @@ body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2
- ; CHECK-LABEL: name: test_lshr_i64_i16
- ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; CHECK: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[AND]](s32)
- ; CHECK: $vgpr0_vgpr1 = COPY [[LSHR]](s64)
+ ; SI-LABEL: name: test_lshr_i64_i16
+ ; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
+ ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[AND]](s32)
+ ; SI: $vgpr0_vgpr1 = COPY [[LSHR]](s64)
+ ; VI-LABEL: name: test_lshr_i64_i16
+ ; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
+ ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[AND]](s32)
+ ; VI: $vgpr0_vgpr1 = COPY [[LSHR]](s64)
+ ; GFX9-LABEL: name: test_lshr_i64_i16
+ ; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
+ ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[AND]](s32)
+ ; GFX9: $vgpr0_vgpr1 = COPY [[LSHR]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
%2:_(s16) = G_TRUNC %1
%3:_(s64) = G_LSHR %0, %2
$vgpr0_vgpr1 = COPY %3
...
+
+---
+name: test_lshr_i16_i32
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+
+ ; SI-LABEL: name: test_lshr_i16_i32
+ ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY1]](s32)
+ ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+ ; SI: $vgpr0 = COPY [[COPY3]](s32)
+ ; VI-LABEL: name: test_lshr_i16_i32
+ ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; VI: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[COPY1]](s32)
+ ; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
+ ; VI: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; GFX9-LABEL: name: test_lshr_i16_i32
+ ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX9: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[COPY1]](s32)
+ ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
+ ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s16) = G_TRUNC %0
+ %3:_(s16) = G_LSHR %2, %1
+ %4:_(s32) = G_ANYEXT %3
+ $vgpr0 = COPY %4
+...
+
+---
+name: test_lshr_i16_i16
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+
+ ; SI-LABEL: name: test_lshr_i16_i16
+ ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[AND1]](s32)
+ ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+ ; SI: $vgpr0 = COPY [[COPY4]](s32)
+ ; VI-LABEL: name: test_lshr_i16_i16
+ ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; VI: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[TRUNC1]](s16)
+ ; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
+ ; VI: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; GFX9-LABEL: name: test_lshr_i16_i16
+ ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; GFX9: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[TRUNC1]](s16)
+ ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
+ ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s16) = G_TRUNC %0
+ %3:_(s16) = G_TRUNC %1
+ %4:_(s16) = G_LSHR %2, %3
+ %5:_(s32) = G_ANYEXT %4
+ $vgpr0 = COPY %5
+...
+
+---
+name: test_lshr_i16_i8
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+
+ ; SI-LABEL: name: test_lshr_i16_i8
+ ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[AND1]](s32)
+ ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+ ; SI: $vgpr0 = COPY [[COPY4]](s32)
+ ; VI-LABEL: name: test_lshr_i16_i8
+ ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; VI: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[AND]](s32)
+ ; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
+ ; VI: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; GFX9-LABEL: name: test_lshr_i16_i8
+ ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; GFX9: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[AND]](s32)
+ ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
+ ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s16) = G_TRUNC %0
+ %3:_(s8) = G_TRUNC %1
+ %4:_(s16) = G_LSHR %2, %3
+ %5:_(s32) = G_ANYEXT %4
+ $vgpr0 = COPY %5
+...
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir?rev=351886&r1=351885&r2=351886&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir Tue Jan 22 14:00:19 2019
@@ -1,5 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefix=SI %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefix=VI %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX9 %s
---
name: test_shl_i32_i32
@@ -12,6 +14,21 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32)
; CHECK: $vgpr0 = COPY [[SHL]](s32)
+ ; SI-LABEL: name: test_shl_i32_i32
+ ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32)
+ ; SI: $vgpr0 = COPY [[SHL]](s32)
+ ; VI-LABEL: name: test_shl_i32_i32
+ ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[SHL]](s32)
+ ; GFX9-LABEL: name: test_shl_i32_i32
+ ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32)
+ ; GFX9: $vgpr0 = COPY [[SHL]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = G_SHL %0, %1
@@ -29,6 +46,24 @@ body: |
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[TRUNC]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[SHL]](s64)
+ ; SI-LABEL: name: test_shl_i64_i64
+ ; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; SI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
+ ; SI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+ ; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[TRUNC]](s32)
+ ; SI: $vgpr0_vgpr1 = COPY [[SHL]](s64)
+ ; VI-LABEL: name: test_shl_i64_i64
+ ; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; VI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
+ ; VI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+ ; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[TRUNC]](s32)
+ ; VI: $vgpr0_vgpr1 = COPY [[SHL]](s64)
+ ; GFX9-LABEL: name: test_shl_i64_i64
+ ; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; GFX9: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
+ ; GFX9: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+ ; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[TRUNC]](s32)
+ ; GFX9: $vgpr0_vgpr1 = COPY [[SHL]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = COPY $vgpr2_vgpr3
%2:_(s64) = G_SHL %0, %1
@@ -45,6 +80,21 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[COPY1]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[SHL]](s64)
+ ; SI-LABEL: name: test_shl_i64_i32
+ ; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
+ ; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[COPY1]](s32)
+ ; SI: $vgpr0_vgpr1 = COPY [[SHL]](s64)
+ ; VI-LABEL: name: test_shl_i64_i32
+ ; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
+ ; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[COPY1]](s32)
+ ; VI: $vgpr0_vgpr1 = COPY [[SHL]](s64)
+ ; GFX9-LABEL: name: test_shl_i64_i32
+ ; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
+ ; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[COPY1]](s32)
+ ; GFX9: $vgpr0_vgpr1 = COPY [[SHL]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
%2:_(s64) = G_SHL %0, %1
@@ -64,9 +114,154 @@ body: |
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[SHL]](s64)
+ ; SI-LABEL: name: test_shl_i64_i16
+ ; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
+ ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s32)
+ ; SI: $vgpr0_vgpr1 = COPY [[SHL]](s64)
+ ; VI-LABEL: name: test_shl_i64_i16
+ ; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
+ ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s32)
+ ; VI: $vgpr0_vgpr1 = COPY [[SHL]](s64)
+ ; GFX9-LABEL: name: test_shl_i64_i16
+ ; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+ ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
+ ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s32)
+ ; GFX9: $vgpr0_vgpr1 = COPY [[SHL]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
%2:_(s16) = G_TRUNC %1
%3:_(s64) = G_SHL %0, %2
$vgpr0_vgpr1 = COPY %3
...
+
+---
+name: test_shl_i16_i32
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+
+ ; SI-LABEL: name: test_shl_i16_i32
+ ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[COPY1]](s32)
+ ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
+ ; SI: $vgpr0 = COPY [[COPY3]](s32)
+ ; VI-LABEL: name: test_shl_i16_i32
+ ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[COPY1]](s32)
+ ; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
+ ; VI: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; GFX9-LABEL: name: test_shl_i16_i32
+ ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[COPY1]](s32)
+ ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
+ ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s16) = G_TRUNC %0
+ %3:_(s16) = G_SHL %2, %1
+ %4:_(s32) = G_ANYEXT %3
+ $vgpr0 = COPY %4
+...
+
+---
+name: test_shl_i16_i16
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+
+ ; SI-LABEL: name: test_shl_i16_i16
+ ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[AND]](s32)
+ ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
+ ; SI: $vgpr0 = COPY [[COPY4]](s32)
+ ; VI-LABEL: name: test_shl_i16_i16
+ ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[TRUNC1]](s16)
+ ; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
+ ; VI: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; GFX9-LABEL: name: test_shl_i16_i16
+ ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[TRUNC1]](s16)
+ ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
+ ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s16) = G_TRUNC %0
+ %3:_(s16) = G_TRUNC %1
+ %4:_(s16) = G_SHL %2, %3
+ %5:_(s32) = G_ANYEXT %4
+ $vgpr0 = COPY %5
+...
+
+---
+name: test_shl_i16_i8
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+
+ ; SI-LABEL: name: test_shl_i16_i8
+ ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+ ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[AND]](s32)
+ ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
+ ; SI: $vgpr0 = COPY [[COPY4]](s32)
+ ; VI-LABEL: name: test_shl_i16_i8
+ ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[AND]](s32)
+ ; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
+ ; VI: $vgpr0 = COPY [[ANYEXT]](s32)
+ ; GFX9-LABEL: name: test_shl_i16_i8
+ ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[AND]](s32)
+ ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
+ ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $vgpr1
+ %2:_(s16) = G_TRUNC %0
+ %3:_(s8) = G_TRUNC %1
+ %4:_(s16) = G_SHL %2, %3
+ %5:_(s32) = G_ANYEXT %4
+ $vgpr0 = COPY %5
+...
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