[llvm] r351856 - GlobalISel: Support narrowing zextload/sextload
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 22 11:02:11 PST 2019
Author: arsenm
Date: Tue Jan 22 11:02:10 2019
New Revision: 351856
URL: http://llvm.org/viewvc/llvm-project?rev=351856&view=rev
Log:
GlobalISel: Support narrowing zextload/sextload
Added:
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-flat.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-global.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-local.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-private.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-flat.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-global.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-local.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-private.mir
Modified:
llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
Modified: llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp?rev=351856&r1=351855&r2=351856&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp Tue Jan 22 11:02:10 2019
@@ -516,6 +516,33 @@ LegalizerHelper::LegalizeResult Legalize
MI.eraseFromParent();
return Legalized;
}
+ case TargetOpcode::G_ZEXTLOAD:
+ case TargetOpcode::G_SEXTLOAD: {
+ bool ZExt = MI.getOpcode() == TargetOpcode::G_ZEXTLOAD;
+ unsigned DstReg = MI.getOperand(0).getReg();
+ unsigned PtrReg = MI.getOperand(1).getReg();
+
+ unsigned TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
+ auto &MMO = **MI.memoperands_begin();
+ if (MMO.getSize() * 8 == NarrowSize) {
+ MIRBuilder.buildLoad(TmpReg, PtrReg, MMO);
+ } else {
+ unsigned ExtLoad = ZExt ? TargetOpcode::G_ZEXTLOAD
+ : TargetOpcode::G_SEXTLOAD;
+ MIRBuilder.buildInstr(ExtLoad)
+ .addDef(TmpReg)
+ .addUse(PtrReg)
+ .addMemOperand(&MMO);
+ }
+
+ if (ZExt)
+ MIRBuilder.buildZExt(DstReg, TmpReg);
+ else
+ MIRBuilder.buildSExt(DstReg, TmpReg);
+
+ MI.eraseFromParent();
+ return Legalized;
+ }
case TargetOpcode::G_STORE: {
// FIXME: add support for when SizeOp0 isn't an exact multiple of
// NarrowSize.
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp?rev=351856&r1=351855&r2=351856&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp Tue Jan 22 11:02:10 2019
@@ -229,6 +229,24 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo
});
+ auto &ExtLoads = getActionDefinitionsBuilder({G_SEXTLOAD, G_ZEXTLOAD})
+ .legalForTypesWithMemSize({
+ {S32, GlobalPtr, 8},
+ {S32, GlobalPtr, 16},
+ {S32, LocalPtr, 8},
+ {S32, LocalPtr, 16},
+ {S32, PrivatePtr, 8},
+ {S32, PrivatePtr, 16}});
+ if (ST.hasFlatAddressSpace()) {
+ ExtLoads.legalForTypesWithMemSize({{S32, FlatPtr, 8},
+ {S32, FlatPtr, 16}});
+ }
+
+ ExtLoads.clampScalar(0, S32, S32)
+ .widenScalarToNextPow2(0)
+ .unsupportedIfMemSizeNotPow2()
+ .lower();
+
auto &Atomics = getActionDefinitionsBuilder(
{G_ATOMICRMW_XCHG, G_ATOMICRMW_ADD, G_ATOMICRMW_SUB,
G_ATOMICRMW_AND, G_ATOMICRMW_OR, G_ATOMICRMW_XOR,
Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-flat.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-flat.mir?rev=351856&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-flat.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-flat.mir Tue Jan 22 11:02:10 2019
@@ -0,0 +1,95 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -o - %s | FileCheck %s
+# RUN: not llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERROR %s
+
+# ERROR: LLVM ERROR: unable to legalize instruction: %2:_(s8) = G_LOAD %0:_(p0) :: (load 1) (in function: test_sextload_flat_i32_i8)
+
+---
+name: test_sextload_flat_i32_i8
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_sextload_flat_i32_i8
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
+ ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1)
+ ; CHECK: $vgpr0 = COPY [[SEXTLOAD]](s32)
+ %0:_(p0) = COPY $vgpr0_vgpr1
+ %1:_(s32) = G_SEXTLOAD %0 :: (load 1, addrspace 0)
+ $vgpr0 = COPY %1
+...
+---
+name: test_sextload_flat_i32_i16
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_sextload_flat_i32_i16
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
+ ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 2)
+ ; CHECK: $vgpr0 = COPY [[SEXTLOAD]](s32)
+ %0:_(p0) = COPY $vgpr0_vgpr1
+ %1:_(s32) = G_SEXTLOAD %0 :: (load 2, addrspace 0)
+ $vgpr0 = COPY %1
+...
+---
+name: test_sextload_flat_i31_i8
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_sextload_flat_i31_i8
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
+ ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SEXTLOAD]](s32)
+ ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
+ %0:_(p0) = COPY $vgpr0_vgpr1
+ %1:_(s31) = G_SEXTLOAD %0 :: (load 1, addrspace 0)
+ %2:_(s32) = G_ANYEXT %1
+ $vgpr0 = COPY %2
+...
+---
+name: test_sextload_flat_i64_i8
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_sextload_flat_i64_i8
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
+ ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1)
+ ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
+ ; CHECK: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
+ %0:_(p0) = COPY $vgpr0_vgpr1
+ %1:_(s64) = G_SEXTLOAD %0 :: (load 1, addrspace 0)
+ $vgpr0_vgpr1 = COPY %1
+...
+---
+name: test_sextload_flat_i64_i16
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_sextload_flat_i64_i16
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
+ ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 2)
+ ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
+ ; CHECK: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
+ %0:_(p0) = COPY $vgpr0_vgpr1
+ %1:_(s64) = G_SEXTLOAD %0 :: (load 2, addrspace 0)
+ $vgpr0_vgpr1 = COPY %1
+...
+---
+name: test_sextload_flat_i64_i32
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_sextload_flat_i64_i32
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
+ ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4)
+ ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[LOAD]](s32)
+ ; CHECK: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
+ %0:_(p0) = COPY $vgpr0_vgpr1
+ %1:_(s64) = G_SEXTLOAD %0 :: (load 4, addrspace 0)
+ $vgpr0_vgpr1 = COPY %1
+...
Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-global.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-global.mir?rev=351856&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-global.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-global.mir Tue Jan 22 11:02:10 2019
@@ -0,0 +1,93 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -o - %s | FileCheck %s
+
+---
+name: test_sextload_global_i32_i8
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_sextload_global_i32_i8
+ ; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load 1, addrspace 1)
+ ; CHECK: $vgpr0 = COPY [[SEXTLOAD]](s32)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(s32) = G_SEXTLOAD %0 :: (load 1, addrspace 1)
+ $vgpr0 = COPY %1
+...
+---
+name: test_sextload_global_i32_i16
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_sextload_global_i32_i16
+ ; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load 2, addrspace 1)
+ ; CHECK: $vgpr0 = COPY [[SEXTLOAD]](s32)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(s32) = G_SEXTLOAD %0 :: (load 2, addrspace 1)
+ $vgpr0 = COPY %1
+...
+---
+name: test_sextload_global_i31_i8
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_sextload_global_i31_i8
+ ; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load 1, addrspace 1)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SEXTLOAD]](s32)
+ ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(s31) = G_SEXTLOAD %0 :: (load 1, addrspace 1)
+ %2:_(s32) = G_ANYEXT %1
+ $vgpr0 = COPY %2
+...
+---
+name: test_sextload_global_i64_i8
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_sextload_global_i64_i8
+ ; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load 1, addrspace 1)
+ ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
+ ; CHECK: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(s64) = G_SEXTLOAD %0 :: (load 1, addrspace 1)
+ $vgpr0_vgpr1 = COPY %1
+...
+---
+name: test_sextload_global_i64_i16
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_sextload_global_i64_i16
+ ; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load 2, addrspace 1)
+ ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
+ ; CHECK: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(s64) = G_SEXTLOAD %0 :: (load 2, addrspace 1)
+ $vgpr0_vgpr1 = COPY %1
+...
+---
+name: test_sextload_global_i64_i32
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_sextload_global_i64_i32
+ ; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load 4, addrspace 1)
+ ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[LOAD]](s32)
+ ; CHECK: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(s64) = G_SEXTLOAD %0 :: (load 4, addrspace 1)
+ $vgpr0_vgpr1 = COPY %1
+...
Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-local.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-local.mir?rev=351856&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-local.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-local.mir Tue Jan 22 11:02:10 2019
@@ -0,0 +1,92 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -o - %s | FileCheck %s
+---
+name: test_sextload_local_i32_i8
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: test_sextload_local_i32_i8
+ ; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
+ ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p3) :: (load 1, addrspace 3)
+ ; CHECK: $vgpr0 = COPY [[SEXTLOAD]](s32)
+ %0:_(p3) = COPY $vgpr0
+ %1:_(s32) = G_SEXTLOAD %0 :: (load 1, addrspace 3)
+ $vgpr0 = COPY %1
+...
+---
+name: test_sextload_local_i32_i16
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: test_sextload_local_i32_i16
+ ; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
+ ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p3) :: (load 2, addrspace 3)
+ ; CHECK: $vgpr0 = COPY [[SEXTLOAD]](s32)
+ %0:_(p3) = COPY $vgpr0
+ %1:_(s32) = G_SEXTLOAD %0 :: (load 2, addrspace 3)
+ $vgpr0 = COPY %1
+...
+---
+name: test_sextload_local_i31_i8
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: test_sextload_local_i31_i8
+ ; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
+ ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p3) :: (load 1, addrspace 3)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SEXTLOAD]](s32)
+ ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
+ %0:_(p3) = COPY $vgpr0
+ %1:_(s31) = G_SEXTLOAD %0 :: (load 1, addrspace 3)
+ %2:_(s32) = G_ANYEXT %1
+ $vgpr0 = COPY %2
+...
+---
+name: test_sextload_local_i64_i8
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: test_sextload_local_i64_i8
+ ; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
+ ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p3) :: (load 1, addrspace 3)
+ ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
+ ; CHECK: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
+ %0:_(p3) = COPY $vgpr0
+ %1:_(s64) = G_SEXTLOAD %0 :: (load 1, addrspace 3)
+ $vgpr0_vgpr1 = COPY %1
+...
+---
+name: test_sextload_local_i64_i16
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: test_sextload_local_i64_i16
+ ; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
+ ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p3) :: (load 2, addrspace 3)
+ ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
+ ; CHECK: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
+ %0:_(p3) = COPY $vgpr0
+ %1:_(s64) = G_SEXTLOAD %0 :: (load 2, addrspace 3)
+ $vgpr0_vgpr1 = COPY %1
+...
+---
+name: test_sextload_local_i64_i32
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_sextload_local_i64_i32
+ ; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
+ ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load 4, addrspace 3)
+ ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[LOAD]](s32)
+ ; CHECK: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
+ %0:_(p3) = COPY $vgpr0
+ %1:_(s64) = G_SEXTLOAD %0 :: (load 4, addrspace 3)
+ $vgpr0_vgpr1 = COPY %1
+...
Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-private.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-private.mir?rev=351856&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-private.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-private.mir Tue Jan 22 11:02:10 2019
@@ -0,0 +1,94 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -o - %s | FileCheck %s
+
+---
+name: test_sextload_private_i32_i8
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: test_sextload_private_i32_i8
+ ; CHECK: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
+ ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p5) :: (load 1, addrspace 5)
+ ; CHECK: $vgpr0 = COPY [[SEXTLOAD]](s32)
+ %0:_(p5) = COPY $vgpr0
+ %1:_(s32) = G_SEXTLOAD %0 :: (load 1, addrspace 5)
+
+ $vgpr0 = COPY %1
+...
+---
+name: test_sextload_private_i32_i16
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: test_sextload_private_i32_i16
+ ; CHECK: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
+ ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p5) :: (load 2, addrspace 5)
+ ; CHECK: $vgpr0 = COPY [[SEXTLOAD]](s32)
+ %0:_(p5) = COPY $vgpr0
+ %1:_(s32) = G_SEXTLOAD %0 :: (load 2, addrspace 5)
+ $vgpr0 = COPY %1
+...
+---
+name: test_sextload_private_i31_i8
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: test_sextload_private_i31_i8
+ ; CHECK: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
+ ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p5) :: (load 1, addrspace 5)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SEXTLOAD]](s32)
+ ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
+ %0:_(p5) = COPY $vgpr0
+ %1:_(s31) = G_SEXTLOAD %0 :: (load 1, addrspace 5)
+ %2:_(s32) = G_ANYEXT %1
+ $vgpr0 = COPY %2
+...
+---
+name: test_sextload_private_i64_i8
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: test_sextload_private_i64_i8
+ ; CHECK: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
+ ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p5) :: (load 1, addrspace 5)
+ ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
+ ; CHECK: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
+ %0:_(p5) = COPY $vgpr0
+ %1:_(s64) = G_SEXTLOAD %0 :: (load 1, addrspace 5)
+ $vgpr0_vgpr1 = COPY %1
+...
+---
+name: test_sextload_private_i64_i16
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: test_sextload_private_i64_i16
+ ; CHECK: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
+ ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p5) :: (load 2, addrspace 5)
+ ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
+ ; CHECK: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
+ %0:_(p5) = COPY $vgpr0
+ %1:_(s64) = G_SEXTLOAD %0 :: (load 2, addrspace 5)
+ $vgpr0_vgpr1 = COPY %1
+...
+---
+name: test_sextload_private_i64_i32
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_sextload_private_i64_i32
+ ; CHECK: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
+ ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load 4, addrspace 5)
+ ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[LOAD]](s32)
+ ; CHECK: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
+ %0:_(p5) = COPY $vgpr0
+ %1:_(s64) = G_SEXTLOAD %0 :: (load 4, addrspace 5)
+ $vgpr0_vgpr1 = COPY %1
+...
Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-flat.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-flat.mir?rev=351856&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-flat.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-flat.mir Tue Jan 22 11:02:10 2019
@@ -0,0 +1,95 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -o - %s | FileCheck %s
+# RUN: not llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERROR %s
+
+# ERROR: LLVM ERROR: unable to legalize instruction: %2:_(s8) = G_LOAD %0:_(p0) :: (load 1) (in function: test_zextload_flat_i32_i8)
+
+---
+name: test_zextload_flat_i32_i8
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_zextload_flat_i32_i8
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
+ ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1)
+ ; CHECK: $vgpr0 = COPY [[ZEXTLOAD]](s32)
+ %0:_(p0) = COPY $vgpr0_vgpr1
+ %1:_(s32) = G_ZEXTLOAD %0 :: (load 1, addrspace 0)
+ $vgpr0 = COPY %1
+...
+---
+name: test_zextload_flat_i32_i16
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_zextload_flat_i32_i16
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
+ ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 2)
+ ; CHECK: $vgpr0 = COPY [[ZEXTLOAD]](s32)
+ %0:_(p0) = COPY $vgpr0_vgpr1
+ %1:_(s32) = G_ZEXTLOAD %0 :: (load 2, addrspace 0)
+ $vgpr0 = COPY %1
+...
+---
+name: test_zextload_flat_i31_i8
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_zextload_flat_i31_i8
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
+ ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ZEXTLOAD]](s32)
+ ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
+ %0:_(p0) = COPY $vgpr0_vgpr1
+ %1:_(s31) = G_ZEXTLOAD %0 :: (load 1, addrspace 0)
+ %2:_(s32) = G_ANYEXT %1
+ $vgpr0 = COPY %2
+...
+---
+name: test_zextload_flat_i64_i8
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_zextload_flat_i64_i8
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
+ ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1)
+ ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32)
+ ; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
+ %0:_(p0) = COPY $vgpr0_vgpr1
+ %1:_(s64) = G_ZEXTLOAD %0 :: (load 1, addrspace 0)
+ $vgpr0_vgpr1 = COPY %1
+...
+---
+name: test_zextload_flat_i64_i16
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_zextload_flat_i64_i16
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
+ ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 2)
+ ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32)
+ ; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
+ %0:_(p0) = COPY $vgpr0_vgpr1
+ %1:_(s64) = G_ZEXTLOAD %0 :: (load 2, addrspace 0)
+ $vgpr0_vgpr1 = COPY %1
+...
+---
+name: test_zextload_flat_i64_i32
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_zextload_flat_i64_i32
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
+ ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4)
+ ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD]](s32)
+ ; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
+ %0:_(p0) = COPY $vgpr0_vgpr1
+ %1:_(s64) = G_ZEXTLOAD %0 :: (load 4, addrspace 0)
+ $vgpr0_vgpr1 = COPY %1
+...
Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-global.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-global.mir?rev=351856&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-global.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-global.mir Tue Jan 22 11:02:10 2019
@@ -0,0 +1,93 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -o - %s | FileCheck %s
+
+---
+name: test_zextload_global_i32_i8
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_zextload_global_i32_i8
+ ; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load 1, addrspace 1)
+ ; CHECK: $vgpr0 = COPY [[ZEXTLOAD]](s32)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(s32) = G_ZEXTLOAD %0 :: (load 1, addrspace 1)
+ $vgpr0 = COPY %1
+...
+---
+name: test_zextload_global_i32_i16
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_zextload_global_i32_i16
+ ; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load 2, addrspace 1)
+ ; CHECK: $vgpr0 = COPY [[ZEXTLOAD]](s32)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(s32) = G_ZEXTLOAD %0 :: (load 2, addrspace 1)
+ $vgpr0 = COPY %1
+...
+---
+name: test_zextload_global_i31_i8
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_zextload_global_i31_i8
+ ; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load 1, addrspace 1)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ZEXTLOAD]](s32)
+ ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(s31) = G_ZEXTLOAD %0 :: (load 1, addrspace 1)
+ %2:_(s32) = G_ANYEXT %1
+ $vgpr0 = COPY %2
+...
+---
+name: test_zextload_global_i64_i8
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_zextload_global_i64_i8
+ ; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load 1, addrspace 1)
+ ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32)
+ ; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(s64) = G_ZEXTLOAD %0 :: (load 1, addrspace 1)
+ $vgpr0_vgpr1 = COPY %1
+...
+---
+name: test_zextload_global_i64_i16
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_zextload_global_i64_i16
+ ; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load 2, addrspace 1)
+ ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32)
+ ; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(s64) = G_ZEXTLOAD %0 :: (load 2, addrspace 1)
+ $vgpr0_vgpr1 = COPY %1
+...
+---
+name: test_zextload_global_i64_i32
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_zextload_global_i64_i32
+ ; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load 4, addrspace 1)
+ ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD]](s32)
+ ; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(s64) = G_ZEXTLOAD %0 :: (load 4, addrspace 1)
+ $vgpr0_vgpr1 = COPY %1
+...
Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-local.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-local.mir?rev=351856&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-local.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-local.mir Tue Jan 22 11:02:10 2019
@@ -0,0 +1,92 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -o - %s | FileCheck %s
+---
+name: test_zextload_local_i32_i8
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: test_zextload_local_i32_i8
+ ; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
+ ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p3) :: (load 1, addrspace 3)
+ ; CHECK: $vgpr0 = COPY [[ZEXTLOAD]](s32)
+ %0:_(p3) = COPY $vgpr0
+ %1:_(s32) = G_ZEXTLOAD %0 :: (load 1, addrspace 3)
+ $vgpr0 = COPY %1
+...
+---
+name: test_zextload_local_i32_i16
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: test_zextload_local_i32_i16
+ ; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
+ ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p3) :: (load 2, addrspace 3)
+ ; CHECK: $vgpr0 = COPY [[ZEXTLOAD]](s32)
+ %0:_(p3) = COPY $vgpr0
+ %1:_(s32) = G_ZEXTLOAD %0 :: (load 2, addrspace 3)
+ $vgpr0 = COPY %1
+...
+---
+name: test_zextload_local_i31_i8
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: test_zextload_local_i31_i8
+ ; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
+ ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p3) :: (load 1, addrspace 3)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ZEXTLOAD]](s32)
+ ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
+ %0:_(p3) = COPY $vgpr0
+ %1:_(s31) = G_ZEXTLOAD %0 :: (load 1, addrspace 3)
+ %2:_(s32) = G_ANYEXT %1
+ $vgpr0 = COPY %2
+...
+---
+name: test_zextload_local_i64_i8
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: test_zextload_local_i64_i8
+ ; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
+ ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p3) :: (load 1, addrspace 3)
+ ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32)
+ ; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
+ %0:_(p3) = COPY $vgpr0
+ %1:_(s64) = G_ZEXTLOAD %0 :: (load 1, addrspace 3)
+ $vgpr0_vgpr1 = COPY %1
+...
+---
+name: test_zextload_local_i64_i16
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: test_zextload_local_i64_i16
+ ; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
+ ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p3) :: (load 2, addrspace 3)
+ ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32)
+ ; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
+ %0:_(p3) = COPY $vgpr0
+ %1:_(s64) = G_ZEXTLOAD %0 :: (load 2, addrspace 3)
+ $vgpr0_vgpr1 = COPY %1
+...
+---
+name: test_zextload_local_i64_i32
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_zextload_local_i64_i32
+ ; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
+ ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load 4, addrspace 3)
+ ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD]](s32)
+ ; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
+ %0:_(p3) = COPY $vgpr0
+ %1:_(s64) = G_ZEXTLOAD %0 :: (load 4, addrspace 3)
+ $vgpr0_vgpr1 = COPY %1
+...
Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-private.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-private.mir?rev=351856&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-private.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-private.mir Tue Jan 22 11:02:10 2019
@@ -0,0 +1,93 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -o - %s | FileCheck %s
+
+---
+name: test_zextload_private_i32_i8
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: test_zextload_private_i32_i8
+ ; CHECK: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
+ ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p5) :: (load 1, addrspace 5)
+ ; CHECK: $vgpr0 = COPY [[ZEXTLOAD]](s32)
+ %0:_(p5) = COPY $vgpr0
+ %1:_(s32) = G_ZEXTLOAD %0 :: (load 1, addrspace 5)
+ $vgpr0 = COPY %1
+...
+---
+name: test_zextload_private_i32_i16
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: test_zextload_private_i32_i16
+ ; CHECK: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
+ ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p5) :: (load 2, addrspace 5)
+ ; CHECK: $vgpr0 = COPY [[ZEXTLOAD]](s32)
+ %0:_(p5) = COPY $vgpr0
+ %1:_(s32) = G_ZEXTLOAD %0 :: (load 2, addrspace 5)
+ $vgpr0 = COPY %1
+...
+---
+name: test_zextload_private_i31_i8
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: test_zextload_private_i31_i8
+ ; CHECK: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
+ ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p5) :: (load 1, addrspace 5)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ZEXTLOAD]](s32)
+ ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
+ %0:_(p5) = COPY $vgpr0
+ %1:_(s31) = G_ZEXTLOAD %0 :: (load 1, addrspace 5)
+ %2:_(s32) = G_ANYEXT %1
+ $vgpr0 = COPY %2
+...
+---
+name: test_zextload_private_i64_i8
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: test_zextload_private_i64_i8
+ ; CHECK: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
+ ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p5) :: (load 1, addrspace 5)
+ ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32)
+ ; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
+ %0:_(p5) = COPY $vgpr0
+ %1:_(s64) = G_ZEXTLOAD %0 :: (load 1, addrspace 5)
+ $vgpr0_vgpr1 = COPY %1
+...
+---
+name: test_zextload_private_i64_i16
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; CHECK-LABEL: name: test_zextload_private_i64_i16
+ ; CHECK: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
+ ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p5) :: (load 2, addrspace 5)
+ ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32)
+ ; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
+ %0:_(p5) = COPY $vgpr0
+ %1:_(s64) = G_ZEXTLOAD %0 :: (load 2, addrspace 5)
+ $vgpr0_vgpr1 = COPY %1
+...
+---
+name: test_zextload_private_i64_i32
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+
+ ; CHECK-LABEL: name: test_zextload_private_i64_i32
+ ; CHECK: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
+ ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load 4, addrspace 5)
+ ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD]](s32)
+ ; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
+ %0:_(p5) = COPY $vgpr0
+ %1:_(s64) = G_ZEXTLOAD %0 :: (load 4, addrspace 5)
+ $vgpr0_vgpr1 = COPY %1
+...
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