[PATCH] D53235: [RISCV] Add RV64F codegen support

[Alex Bradbury via Phabricator via llvm-commits]

asb updated this revision to Diff 182851.
asb marked an inline comment as done.
asb added a comment.

Updated to address all outstanding feedback. The combines are now properly guarded and a test case verified this. I've removed the logic that prefers fcvt.w[u].s and added exhaustive tests for sext/zext/aext of the results.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D53235/new/

https://reviews.llvm.org/D53235

Files:
  lib/Target/RISCV/RISCVISelLowering.cpp
  lib/Target/RISCV/RISCVISelLowering.h
  lib/Target/RISCV/RISCVInstrInfoF.td
  test/CodeGen/RISCV/float-arith.ll
  test/CodeGen/RISCV/float-br-fcmp.ll
  test/CodeGen/RISCV/float-convert.ll
  test/CodeGen/RISCV/float-fcmp.ll
  test/CodeGen/RISCV/float-imm.ll
  test/CodeGen/RISCV/float-mem.ll
  test/CodeGen/RISCV/float-select-fcmp.ll
  test/CodeGen/RISCV/rv32i-rv64i-float-double.ll
  test/CodeGen/RISCV/rv64f-float-convert.ll

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