[llvm] r351692 - AMDGPU/GlobalISel: Regbank select for fpext

[Matt Arsenault via llvm-commits]

Author: arsenm
Date: Sun Jan 20 10:35:41 2019
New Revision: 351692

URL: http://llvm.org/viewvc/llvm-project?rev=351692&view=rev
Log:
AMDGPU/GlobalISel: Regbank select for fpext

Added:
    llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fpext.mir
Modified:
    llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp?rev=351692&r1=351691&r2=351692&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp Sun Jan 20 10:35:41 2019
@@ -433,6 +433,7 @@ AMDGPURegisterBankInfo::getInstrMapping(
   case AMDGPU::G_SITOFP:
   case AMDGPU::G_UITOFP:
   case AMDGPU::G_FPTRUNC:
+  case AMDGPU::G_FPEXT:
   case AMDGPU::G_FEXP2:
   case AMDGPU::G_FLOG2:
   case AMDGPU::G_INTRINSIC_TRUNC:

Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fpext.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fpext.mir?rev=351692&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fpext.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fpext.mir Sun Jan 20 10:35:41 2019
@@ -0,0 +1,31 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+
+---
+name: fpext_s
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0
+    ; CHECK-LABEL: name: fpext_s
+    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+    ; CHECK: [[FPEXT:%[0-9]+]]:vgpr(s64) = G_FPEXT [[COPY]](s32)
+    %0:_(s32) = COPY $sgpr0
+    %1:_(s64) = G_FPEXT %0
+...
+
+---
+name: fpext_v
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0
+    ; CHECK-LABEL: name: fpext_v
+    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+    ; CHECK: [[FPEXT:%[0-9]+]]:vgpr(s64) = G_FPEXT [[COPY]](s32)
+    %0:_(s32) = COPY $vgpr0
+    %1:_(s64) = G_FPEXT %0
+...