[llvm] r351584 - GlobalISel: Verify g_zextload and g_sextload

[Amara Emerson via llvm-commits]

Hi Matt,

This assert seems to be triggering on the aarch64 bot. I’m going to revert it for now while we investigate.

Thanks,
Amara

> On Jan 18, 2019, at 12:17 PM, Matt Arsenault via llvm-commits <llvm-commits at lists.llvm.org> wrote:
> 
> Author: arsenm
> Date: Fri Jan 18 12:17:37 2019
> New Revision: 351584
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=351584&view=rev
> Log:
> GlobalISel: Verify g_zextload and g_sextload
> 
> Added:
>    llvm/trunk/test/CodeGen/MIR/AArch64/invalid-extload.mir
> Modified:
>    llvm/trunk/lib/CodeGen/MachineVerifier.cpp
> 
> Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=351584&r1=351583&r2=351584&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original)
> +++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Fri Jan 18 12:17:37 2019
> @@ -986,11 +986,24 @@ void MachineVerifier::visitMachineInstrB
>     break;
>   case TargetOpcode::G_LOAD:
>   case TargetOpcode::G_STORE:
> +  case TargetOpcode::G_ZEXTLOAD:
> +  case TargetOpcode::G_SEXTLOAD:
>     // Generic loads and stores must have a single MachineMemOperand
>     // describing that access.
> -    if (!MI->hasOneMemOperand())
> +    if (!MI->hasOneMemOperand()) {
>       report("Generic instruction accessing memory must have one mem operand",
>              MI);
> +    } else {
> +      if (MI->getOpcode() == TargetOpcode::G_ZEXTLOAD ||
> +          MI->getOpcode() == TargetOpcode::G_SEXTLOAD) {
> +        const MachineMemOperand &MMO = **MI->memoperands_begin();
> +        LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
> +        if (MMO.getSize() * 8 >= DstTy.getSizeInBits()) {
> +          report("Generic extload must have a narrower memory type", MI);
> +        }
> +      }
> +    }
> +
>     break;
>   case TargetOpcode::G_PHI: {
>     LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
> 
> Added: llvm/trunk/test/CodeGen/MIR/AArch64/invalid-extload.mir
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AArch64/invalid-extload.mir?rev=351584&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/MIR/AArch64/invalid-extload.mir (added)
> +++ llvm/trunk/test/CodeGen/MIR/AArch64/invalid-extload.mir Fri Jan 18 12:17:37 2019
> @@ -0,0 +1,23 @@
> +# RUN: not llc -mtriple=aarch64-none-linux-gnu -run-pass none -o - %s 2>&1 | FileCheck %s
> +
> +# CHECK: *** Bad machine code: Generic extload must have a narrower memory type ***
> +# CHECK: *** Bad machine code: Generic extload must have a narrower memory type ***
> +# CHECK: *** Bad machine code: Generic extload must have a narrower memory type ***
> +# CHECK: *** Bad machine code: Generic extload must have a narrower memory type ***
> +# CHECK: *** Bad machine code: Generic instruction accessing memory must have one mem operand ***
> +# CHECK: *** Bad machine code: Generic instruction accessing memory must have one mem operand ***
> +
> +---
> +name: invalid_extload_memory_sizes
> +body: |
> +  bb.0:
> +
> +    %0:_(p0) = COPY $x0
> +    %1:_(s64) = G_ZEXTLOAD %0(p0) :: (load 8)
> +    %2:_(s64) = G_ZEXTLOAD %0(p0) :: (load 16)
> +    %3:_(s64) = G_SEXTLOAD %0(p0) :: (load 8)
> +    %4:_(s64) = G_SEXTLOAD %0(p0) :: (load 16)
> +    %5:_(s64) = G_ZEXTLOAD %0(p0)
> +    %6:_(s64) = G_SEXTLOAD %0(p0)
> +
> +...
> 
> 
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