[PATCH] D56864: [x86] vectorize cast ops in lowering to avoid register file transfers

[Sanjay Patel via Phabricator via llvm-commits]

spatel created this revision.
spatel added reviewers: RKSimon, craig.topper, lebedev.ri, andreadb.
Herald added a subscriber: mcrosier.

The proposal in D56796 <https://reviews.llvm.org/D56796> may cross the line because we're trying to avoid vectorization transforms in generic DAG combining. So this is an alternate, later, x86-specific translation of that patch.

I've avoided all potentially controversial transforms such as extraction from a non-zero element of a vector, so all test diffs here are a clear win AFAIK.


https://reviews.llvm.org/D56864

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/known-bits-vector.ll
  test/CodeGen/X86/known-signbits-vector.ll
  test/CodeGen/X86/vec_int_to_fp.ll

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