[PATCH] D56082: [X86][SLP] Enable SLP vectorization for 128-bit horizontal X86 instructions (add, sub)

[Anton Afanasyev via Phabricator via llvm-commits]

anton-afanasyev added a comment.

In D56082#1360129 <https://reviews.llvm.org/D56082#1360129>, @craig.topper wrote:

> There are a lot of test changes here that have nothing to do with the add/sub operations mentioned in the title. How do we know these changes are good? Was any benchmarking done with this patch?


As for the test changes not related to add/sub operations (horizontal ops), they are mostly caused by partial vectorization (like `fmul <2 x float>`). Firstly I tried to escape this by adding additional cost for all 64-bit ops not concerned with horizontal ones, but it looks dirty and unnecessary since partial vectorization are fair optimization as well (if `Cost < 0`).


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