[PATCH] D56810: [Mem2Reg] Enable promotion for bitcastable load/store values

[Sergey Dmitriev via Phabricator via llvm-commits]

sdmitriev created this revision.
sdmitriev added a reviewer: andrew.w.kaylor.
Herald added subscribers: llvm-commits, jfb.

This patch enables Mem2Reg to handle loads/stores from/to bitcasted alloca
values as long as the loaded/stored value is bitcastable to the allocated
type (see example below). Such instruction sequences can be introduced by
the InstCombine pass as part of the load canonicalization.

    
  %f = alloca float, align 4
  ...
  %0 = getelementptr inbounds float, float* %A, i64 %idx
  %1 = bitcast float* %0 to i32*
  %2 = load i32, i32* %1, align 4
  %3 = bitcast float* %f to i32*
  store i32 %2, i32* %3, align 4


Repository:
  rL LLVM

https://reviews.llvm.org/D56810

Files:
  lib/Transforms/Utils/PromoteMemoryToRegister.cpp
  test/Transforms/Mem2Reg/bitcast.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D56810.182148.patch
Type: text/x-patch
Size: 35250 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20190116/8431f268/attachment.bin>