[PATCH] D56082: [X86][SLP] Enable SLP vectorization for 128-bit horizontal X86 instructions (add, sub)

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added inline comments.


================
Comment at: lib/Target/X86/X86TargetTransformInfo.cpp:150-154
+// MMX 64-bit registers and horizontal 128-bit operations.
+// This also allows vectorizer to use partial vector operations.
+unsigned X86TTIImpl::getMinVectorRegisterBitWidth() const {
+  return 64;
+}
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anton-afanasyev wrote:
> lebedev.ri wrote:
> > I lack context, but will this also handle e.g. `_mm_hadd_epi16()` ?
> Yes, phaddw is also handled.
Then i don't understand the function name. (yes, i understand that it is a pre-existing hook)
`_mm_hadd_epi16()` operates on `i16`, how come `64` is the right pick here?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D56082/new/

https://reviews.llvm.org/D56082