[PATCH] D56682: [GlobalISel][AArch64] Add isel support for FP16 vector @llvm.ceil

[Jessica Paquette via Phabricator via llvm-commits]

paquette created this revision.
paquette added a reviewer: aemerson.
Herald added subscribers: kristof.beyls, javed.absar, rovka.

This patch adds support for vector @llvm.ceil intrinsics when full 16 bit floating point support isn't available.

To do this, this patch...

- Implements basic isel for G_UNMERGE_VALUES
- Teaches the legalizer about 16 bit floats
- Teaches AArch64RegisterBankInfo to respect floating point registers on G_BUILD_VECTOR and G_UNMERGE_VALUES
- Teaches selectCopy about 16-bit floating point vectors

It also adds

- A legalizer test for the 16-bit vector ceil which verifies that we create a G_UNMERGE_VALUES and G_BUILD_VECTOR when full fp16 isn't supported
- An instruction selection test which makes sure we lower to G_FCEIL when full fp16 is supported
- A test for selecting G_UNMERGE_VALUES

And also updates arm64-vfloatintrinsics.ll to show that the new ceiling types work as expected.


https://reviews.llvm.org/D56682

Files:
  lib/CodeGen/GlobalISel/LegalizerHelper.cpp
  lib/Target/AArch64/AArch64InstructionSelector.cpp
  lib/Target/AArch64/AArch64LegalizerInfo.cpp
  lib/Target/AArch64/AArch64RegisterBankInfo.cpp
  test/CodeGen/AArch64/GlobalISel/legalize-ceil.mir
  test/CodeGen/AArch64/GlobalISel/select-ceil.mir
  test/CodeGen/AArch64/GlobalISel/select-unmerge.mir
  test/CodeGen/AArch64/arm64-vfloatintrinsics.ll

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