[PATCH] D53235: [RISCV] Add RV64F codegen support

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


================
Comment at: lib/Target/RISCV/RISCVISelDAGToDAG.cpp:161
+  }
+  case ISD::AssertSext: {
+    if (!Subtarget->is64Bit())
----------------
asb wrote:
> efriedma wrote:
> > The point of this is to try to generate a "narrower" FP_TO_SINT where possible?  Does this transform actually improve performance?
> The alternative is fcvt.l.s + sign-extension of the result. Just emitting fcvt.w.s is fewer instructions.
I still don't follow; AssertSext doesn't lower to any instructions.  So the alternative is just the one fcvt.l.s.  (The "trick" here is that fptosi returns poison if the result would be out of range.)


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D53235/new/

https://reviews.llvm.org/D53235